Nanominer - Modular FPGA Mining Platform

[wondermine]

There is already a mining script using a serial connection to FPGA ...

https://bitcointalk.org/index.php?topic=62823.0

Let me restate. Would someone like to work with me to get that interfacing with the FPGA. I'm not good with python, and I'm not sure exactly how that wants its data.  It's not just a matter of slapping serial on there and linking it up with the script, though I'm sure it's a great script.

----------------------------------
I'm squeezing 26.5MH/s out of a Nano with the latest design; that's verified accepted shares.  I need to run the compile again with subscription edition, because this fitting is really poor, I'll have better numbers for your tomorrow.  I've also got some rewriting to do that'll increase that speed. This Quartus web edition is really crippled.

In looking around a little, I've noticed prices on FPGA standalone chips, Cyclone IV E series, but larger than the Nano's chip by a little more than 2x.  The chips are about $85 a pop, and would require another $30-45 in circuitry/board/etc, so about $130 but it would mean some design and manufacture on our part.  That and the shipping would be cheaper than anyone else's, since I'd do the mass orders and ship cheaply for everyone.

Using the aforementioned chip and a custom board you could get 53MH/s (likely more, but I know you guys like verified numbers) for $130 at 0.5W max.  Is that something that I should consider pursuing? I have a friend who's excellent at circuit design and expressed some interest, but I'd need to know there was interest.  I know the number isn't dazzling, though it will likely be at least 60, but that power figure and the fact that the board would be a couple inches by a couple inches is very attractive when compared to PCs...

Let me know.  Either way hopefully these improving numbers are good indicators to you all; I haven't exhausted all the optimizations I've been working on, so more better numbers to come.

[Inspector 2211]

>consider pursuing?

Frankly, no.
One could simply copy the ZTEX design, which is available under the GPL license, if memory serves, spend a tad over $200 per board (not for 2 or 10, but, say, for 50 or 100) and achieve a tad more than 200 MH/s.  $1 per MH/s. Thus, I'd advise against pursuing a $2 per MH/s design.

[Inspector 2211]

There's also a guy going by the name of eldentyrell, who has managed to fit 3 SHA-256es (3 half-miners) into a Spartan6-150, but as of yet, he has not disclosed the clock rate yet, and it is unclear whether he is willing to put the bitstream into the public domain, something that Stefan of ZTEX has done. Something that the designer of the Icarus board has also done.

If you want to be a hero here, follow in eldentyrell's footsteps, squeeze 3 SHA-256 into a Spartan6-150 and put design and bitstream into the public domain.
And/or improve the Icarus implementation.
And/or improve the ZTEX implementation.

[Dexter770221]

So, what happend with 75+ MH/s from 22k part? 60 from twice a price is NOT competitive. 22k parts are avaible in TQFP packages, Easy to solder, design of 2layer PCB is also easy. Only that makes sense.

[makomk]

I don't understand.
If the h value of the midstate is 0x5be0cd19, then the next h value that is added to it must be exactly 0xa41f32e7 to get the 0x00000000 value to make a valid share at difficulty 1.
Isn't that a way bigger advantage? Now you know for sure you got a value you want and not some strange percentage.
I assume no pools use shares less than difficulty 1 and for mining in pools with difficulty greater than 1 it should be easy for the miner software on the host computer to check if the share with difficulty 1 is also valid for the pool with difficulty x.

Not only that, but some code out there already takes advantage of this particular optimization. For example, I know that my variant of fpgaminer's code does so for fully-unrolled miners - in fact it totally omits the last three SHA-256 rounds - and it looks like ztex's code (which is what most people are using these days) does too in all its variants.

Edit:

I'm squeezing 26.5MH/s out of a Nano with the latest design; that's verified accepted shares.  I need to run the compile again with subscription edition, because this fitting is really poor, I'll have better numbers for your tomorrow.  I've also got some rewriting to do that'll increase that speed. This Quartus web edition is really crippled.

Ooh, very impressive - will be interesting to see what you manage to get up to in the end.

[Wandering Albatross]

It seems that the pain will only propagate using all these proprietary tools. Are there any open, linux SDKs for this hardware? Reinventing the wheel is not cost efficient.

For example for spartan6 there is:
www.petalogix.com/about/supported-fpga-and-cpu-families

[lame.duck]

It seems that the pain will only propagate using all these proprietary tools. Are there any open, linux SDKs for this hardware? Reinventing the wheel is not cost efficient.

For example for spartan6 there is:
www.petalogix.com/about/supported-fpga-and-cpu-families

This are not the tools required to generate FPGA bitstreams. This ist a (as far i see) an IDE to develop Software for Soft and hard-cores.

[Wandering Albatross]

This are not the tools required to generate FPGA bitstreams. This ist a (as far i see) an IDE to develop Software for Soft and hard-cores.

I misread the offering, I thought they had a free version and a commercial version but you have to go through sales to get the SDK.
And it's not clear what they offer in the SDK. I got to that site from another site that made it sound like something different.

[rph]

5 ns, that is a delay straight from the 70s. A TTL technology-like delay. Certainly we can do better than that?!?

FPGA fabric frequencies have been stuck around 200-300MHz for 10+ years
because, while the LUTs are still getting (slightly) faster, the wires between them aren't.

So you have to go wider instead of faster.

-rph

[Inspector 2211]

5 ns, that is a delay straight from the 70s. A TTL technology-like delay. Certainly we can do better than that?!?

FPGA fabric frequencies have been stuck around 200-300MHz for 10+ years
because, while the LUTs are still getting (slightly) faster, the wires between them aren't.

So you have to go wider instead of faster.

-rph

As far as I understand, long wires don't come into the picture much when you enter a counter-pattern on the left, let it percolate through 128 stages and then wind up with a yes/no value on the right. Rather, I think the 5ns clock cycle is due to two sequential 32 bit additions, implemented with ripple carries. 
The irony is that FPGAs have hardware multipliers (in the DSP blocks), but few or no hardware adders. (I think there is an adder in each DSP block also, feeding into the multiplier, but there are not enough of them.)

[Wandering Albatross]

Does this project have a greenlight? Is this a college project too? How much funding do you have so far?

[wondermine]

Sorry for the delays in update, it's exam time and I'm pretty busy.
To answer a few questions:

Regarding "reinventing the wheel": I'm all for working from what there is, but I'm doing this project partially as a way to augment my understanding of circuit design, HDL design, cryptography/analysis, and mathematics.  I will build my own IP for things if I deem it educational.  Will that slow things down? Sometimes. Will that also potentially improve the final product? Possibly. I'm not doing this project because it's so lucrative... it's not.  It's educational.

Regarding when you can see the code: I'll be uploading it I have in entirety to my website once I'm finished exams, it just needs to be commented and some translated into VHDL from Verilog.

Regarding whether this project is official or has a greenlight: Simply put, nope.  This is entirely of my own volition, all funding is from donations, and the time is what I can spare when I'm not designing vehicle and robotics control systems, doing homework, or attempting to have a social life.

Another comment I'd like to make regarding the design of Nanominer:  This project will be the best I/we can make it; however I know there are a lot of people working on FPGA mining technology, and I may well not have the technical edge; I certainly don't have the time/funding.  My hope is, despite the possible disadvantages, is to have it be fully open-source and extremely well documented, I'd love to make something that any of you can download and modify to your liking or improve upon with ease, Bitcoin is a great platform on which to learn a lot of topics.  The "edge" I hope for in this project is a mathematical one, which may be a pipe dream, or never work, and I won't let it get in the way of Nanominer being what we want it to, but I will put time into mathematical research, even if it seems like a dead end to people.

If you're looking for a good, solid community project you can help work on and improve, with someone at the head who's willing to learn and improve, this is for you.  I'm not here to make money, I'm here to learn.  If that bothers you, there are a lot of other projects for FPGA who are interested in profits.

I'll keep you all posted, and I'll let you know when exams are finished, that should give me a decent amount of time to get things going.

[Wandering Albatross]

Regarding whether this project is official or has a greenlight: Simply put, nope.

Thanks for the update and good luck on exams. I'm just a curious bystander to all that is BTC. I find the FPGA solution to be the most interesting part. I think you know that the BTC world has tons of frauds and many on these forums. So the questions are partly a legit-test too.

FPGA combined with free energy sources will dominate the mining world. I'm sure someone's working on a mining asic and they may be able to go faster and use less power but the price will be high.

[Transisto]

In your first post you claim "I have a modified core running on a Stratix IV at 3.6GH/s"

I do not ask for anything more than that. Is this part true ?

How much would it cost me to have your software that run on it ?

[ZPK]

who test this ?
http://www.buyincoins.com/details/arduino-nano-v3-0-avr-atmega328-p-20au-moudle-board-with-usb-cable-product-10178.html

[pieppiep]

who test this ?
http://www.buyincoins.com/details/arduino-nano-v3-0-avr-atmega328-p-20au-moudle-board-with-usb-cable-product-10178.html

What do you want to know about it?
It's not a FPGA and if it is possible to mine on it, it would be very slow and no networksupport on it.
Maybe a normal pc can mine faster in just the time it takes to talk to this thing.

[rph]

Rather, I think the 5ns clock cycle is due to two sequential 32 bit additions, implemented with ripple carries. 

In Spartan6, the ternary addition uses only ~2ns. The routing delays - and ISE's inability to
consistently minimize them - are a bigger problem.

-rph

[wondermine]

In your first post you claim "I have a modified core running on a Stratix IV at 3.6GH/s"

I do not ask for anything more than that. Is this part true ?

How much would it cost me to have your software that run on it ?

You can find your answer by reading through the posts or re-checking the first post, or my site.  The FPGA currently is running at 800MH/s verified.
As far as it costing you, the software is free, and like I've said, I'll be publishing it after crunch time is over at school.  Donations, however, are always welcome.

who test this ?
http://www.buyincoins.com/details/arduino-nano-v3-0-avr-atmega328-p-20au-moudle-board-with-usb-cable-product-10178.html

Not related to BTC mining, but I have about 12 Arduinae among other microcontroller dev boards (PIC, ARM) here or in my lab.
They're great boards, they will not, like the man says, generate BTC though.  If you have a specific question feel free to email me; this thread should probably be kept to BTC talk.

Still doing exams, thought I'd pop my head up.

[Inspector 2211]

The least expensive Stratix IV kit seems to be Terasic's DE4, which retails for $2,995
Currently wondermine gets 800 MH/s on it (but obviously, future improvements in hash rate are a distinct possibility).
But right now, that's about $3.75 per MH/s. 

BFL Single: $600 for 800 MH/s, which is about $0.75 per MH/s.

I guess, I'll take the BFL Single (in fact, I just ordered four more of them this morning). 

[pazor]

@inspector

can you inform us when you get the miner ?


@wondermine

can you tell us when we can expect an working fpga miner to buy ?

greetings
pazor