I realise this is probably unlikely to happen, but I've joined as I'd really like some advice from TheSeven if they have the time. I have the same XUPV5 -LZ110T FPGA board as you (I think, judging by a picture I saw) and I'm trying to get the VHDL miner to work.
Firstly, I could only get it to synthesize when I reduced the depth, it was 6, I now have it at 2, it might work higher but I haven't tested it yet, is this to be expected? Also, what should I connect the clk_in port to? I had to it connected to CLK_33MHZ_FPGA (AH17) but got errors from the python program saying that it timed out waiting for a response. I then read the post about adjusting the UART clock divider, which I attempted to do based on the formulas you posted, but then got the "got bad message from fpga: 28" error.
Basically, am I connecting the right pin to clk_in? I'm just trying it with CLK_27MHZ_FPGA now. Is there anything else I should be changing, such as CLKIN_PERIOD in top.vhd? I have tried changing it to 30ns (i.e. 1/33MHz-ish) with no joy.
Hopefully you'll read this, or someone else might help.
Thanks for reading..