Nanominer Announcement

[Jason]

Yes, perhaps an expansion card with LCD capability could be arranged, no they are not that expensive.  Perhaps I will add a communications port for peripherals that can be purchased seperately on these counts (LCD, SD, etc.) without having to include them in the project and make the whole thing more expensive.  I will not, however, impose features on people.  It will be barebones, then will have the capability to expand with whatever fancy parts you'd like to have.

Then what would distinguish your proposed system from the X6500, Icarus, or Ztex boards already out there?  It seems to me you are just re-inventing the wheel with what you propose.  That's great if you can manage to do it for less than they are charging, though I suspect that will not be so easy. 

[rjk]

Yes, perhaps an expansion card with LCD capability could be arranged, no they are not that expensive.  Perhaps I will add a communications port for peripherals that can be purchased seperately on these counts (LCD, SD, etc.) without having to include them in the project and make the whole thing more expensive.  I will not, however, impose features on people.  It will be barebones, then will have the capability to expand with whatever fancy parts you'd like to have.

Then what would distinguish your proposed system from the X6500, Icarus, or Ztex boards already out there?  It seems to me you are just re-inventing the wheel with what you propose.  That's great if you can manage to do it for less than they are charging, though I suspect that will not be so easy. 

None of the other boards have Ethernet, and only some offer any kind of expansion - not to mention that this one is the first to offer any sort of modular expansion.

[lame.duck]

None of the other boards have Ethernet, and only some offer any kind of expansion - not to mention that this one is the first to offer any sort of modular expansion.

Well. the icarus are some sort of expansion boards, there is only the mainboard missing, and i bet ngzhang would be able to design such a board.

[wondermine]

From the sounds of it, you'd be willing to pay a little extra for some bonus functionality.  Let me go back to the drawing board a little bit, and see what I can do about offering something that does it all on-chip, so that you can plug it into your router etc. at home and have it mine without a host.  USB will remain available for those who don't have an extra port on the router, and WiFi will be an *option* too, though it'll tack on a little money.
After some review, I'd like to make it clear that there will be a maximum of 4 expansion boards per main board. (Note that a specialized jumper tech is in the works, this number may increase)  This will be a limit imposed by firmware, and you can modify it if you like, but it will be unsupported.  The price of a main board won't be *that* much more, so getting 1 GH/s per mainboard-and-four-expansions isn't too bad for the price.  Not to mention the fact that it's modular.
As far as what my offering has that others don't, the modularity and Ethernet, as someone mentioned, are a plus.  Now, standalone functionality and WiFi capability will also be a bonus.  All of this in addition to the fact that my prices are competitive, if not cheaper than the going rate for FPGA miners.
Let me lay down a schematic that allows for standalone operation and I'll let everyone know what the price is looking like, so y'all have a better idea.  Spoiler: It will be more expensive given that it is standalone, but I can tell that that would be convenient for some of you, so I'll check it out.
Keep an eye on the post, and thanks for your comments!

[wondermine]

How does $325 USD + shipping sound for the main board, and $275 USD + shipping for expansions?

Features (Main Board):
-LCD Display
-200 MH/s Hashrate
-Xilinx Spartan-6 XC6SLX150 FPGA
-Standalone Functionality
-More than capable of running ucLinux (2MB Flash, 8MB SDRAM, ARM M4-Cortex MCU)
-Modular Expandability
-Reconfigurable to do as you like, not just BTC mining
-USB and Ethernet interfaces
-Maximum 4 Expansions per Main Board (Firmware Imposed)

[rjk]

How does $325 USD + shipping sound for the main board, and $275 USD + shipping for expansions?

Features (Main Board):
-LCD Display
-200 MH/s Hashrate
-Xilinx Spartan-6 XC6SLX150 FPGA
-Standalone Functionality
-More than capable of running ucLinux (2MB Flash, 8MB SDRAM, ARM M4-Cortex MCU)
-Modular Expandability
-Reconfigurable to do as you like, not just BTC mining
-USB and Ethernet interfaces
-Maximum 4 Expansions per Main Board (Firmware Imposed)

Certainly seems competitive, at least compared to the current gen products available. What is the expected power budget, including the additional components?

So is it mainboard + 3 addons for a total of 4, or is it + 4 addons for a total of 5? If it is a total of 5, it would be 1Ghash for $1425 + shipping.

[wondermine]

How does $325 USD + shipping sound for the main board, and $275 USD + shipping for expansions?

Features (Main Board):
-LCD Display
-200 MH/s Hashrate
-Xilinx Spartan-6 XC6SLX150 FPGA
-Standalone Functionality
-More than capable of running ucLinux (2MB Flash, 8MB SDRAM, ARM M4-Cortex MCU)
-Modular Expandability
-Reconfigurable to do as you like, not just BTC mining
-USB and Ethernet interfaces
-Maximum 4 Expansions per Main Board (Firmware Imposed)

Certainly seems competitive, at least compared to the current gen products available. What is the expected power budget, including the additional components?

So is it mainboard + 3 addons for a total of 4, or is it + 4 addons for a total of 5? If it is a total of 5, it would be 1Ghash for $1425 + shipping.

1 Mainboard, +4 Addons.
Expected power budget is 11W/board, but I'll try to cut down if possible.

[wondermine]

Unless the cost is negligible I think the display should be optional.

Barebones standalone functionality is ideal.  Everything else should be modularly optional.

I'd agree with you but it's not the best screen around, the cost is certainly negligible.  It's more so that someone using it as a standalone device can see what's going on with their miner without having to plug it in anywhere.

[rjk]

Unless the cost is negligible I think the display should be optional.

Barebones standalone functionality is ideal.  Everything else should be modularly optional.

I'd agree with you but it's not the best screen around, the cost is certainly negligible.  It's more so that someone using it as a standalone device can see what's going on with their miner without having to plug it in anywhere.

Yeah as long as it isn't a $25 part, I'd find it handy to have since I wouldn't be using a host system to run it.

[norulezapply]

Watching...

PS I'd rather have a "as-cheap-and-barebones-as-possible" FPGA.

No fancy screens or built in ethernet or cgminer. Just a bare FPGA board that I can connect with USB.

[rjk]

Watching...

PS I'd rather have a "as-cheap-and-barebones-as-possible" FPGA.

No fancy screens or built in ethernet or cgminer. Just a bare FPGA board that I can connect with USB.

Ztex?

[norulezapply]

Watching...

PS I'd rather have a "as-cheap-and-barebones-as-possible" FPGA.

No fancy screens or built in ethernet or cgminer. Just a bare FPGA board that I can connect with USB.

Ztex?

Nanominer seems like it's going to be a cheaper option than ztex is unless I'm looking at it wrong

[rjk]

Watching...

PS I'd rather have a "as-cheap-and-barebones-as-possible" FPGA.

No fancy screens or built in ethernet or cgminer. Just a bare FPGA board that I can connect with USB.

Ztex?

Nanominer seems like it's going to be a cheaper option than ztex is unless I'm looking at it wrong

Quite so. But if you want fewer features at a higher price, Ztex is the way to go.

[JWU42]

Liking what I am seeing - wish there was MOAR hashes though... 

[tgmarks]

Can't wait to see news of a functioning prototype.  Love the expandable modular nature with additional boards.

[wondermine]

I've got a preliminary Nanominer bitstream.  I'd like to be clear about whether it works: the digester is functional and has been tested with fpgaminer's code.  The rest of it looks fine in simulation, but the final product's *control circuitry* (i.e. state machines) may need fixing.  That said, the digester, which is the heart of it all *definitely works* at the size and performance I'm quoting here.  To prove this to everyone, I'm linking a .zip with the design files so you can see what I've been working on.  I only guarentee the digester (working_sha256.vhd) works 100% but so far the rest looks good.
Also that digester is sitting in for a better, more pipelined one that is smaller and performs better, but is still in the works.  I thought I'd let you all see something that actually can produce bitcoin.  The *current* specs are as follows:

Note:
-Compiled with Web Edition, I need to go to school and put this through the subscription one
-The fmax *varies* with the chip
-I do not know if this is analogous to Xilinx logic consumption; if it is, things are going well for all of us.
-The code is run preserving nodes with lost fanout because I don't have decent input and Quartus wants to synthesize away the duplicate cores (which are actually working in parallel
-I'm posting this for your interest, peace of mind, and maybe to whet your appetite, this is not to be scrutinized; it's a work in progress.  Constructive ideas, go for it, but picking the hell out of my design really won't do much good
-The new core is very promising, I expect a ~15% increase in performance in the next week

So:
Control Circuit Logic Consumption: 289 LC Registers (One per chip)
Core Logic Consumption: 1844 LC Registers (Iterative, as many as you like)
Cycles per Hash: 128
fmax @ Speed Grade 6: 201.73 MHz  (Cyclone IV)
Hashrate: 1.58MH/core
--edited to fix size--

So, it's not completely groundbreaking, yet, but there's a lot more where this came from.  This little announcement is more to say that I'm working, and this thing is coming.  I have my core less than 800 LEs (which would mean a DE0 hashrate of >40MH/s, and a significant improvement past 210MH/s on a Spartan-6), but I need to get timing logistics down, so more to come.

In the meantime, I'll post the VHDL for you all.  As always, donations are welcome, I do spend a hell of a lot of time on this and the way things are looking I'll break more records than just the DE0-Nano speed record.  I haven't broken the 210MH barrier yet, but soon enough, I just need to put a little more time into it.

Edit: By the way, it's not commented, and it's got an SDC but no QPF or anything, just straight VHDL.  All rights reserved me etc. cheers!

[mrb]

Interesting. Assuming your design can be ported from the Cyclone IV to the Stratix III, an EP3SL200 at 213MHz with 250 of your 800-LE cores would produce 416 Mhash/s. That would account exactly for the performance of the BitForce Single (rumored to be two EP3SL200 chips = 832 Mhash/s)...

[lame.duck]

Hm, how did you get the number of  Logic cells without having a qpf and qsf file?
Why do you design a control logic  with 288 IOs for a chip with only 167 usable IO pins (153 usable on the DE0 (including th pins for RAM etc.).

I tried to test compile the design for a cyclone IV with 30 kLE but fiting failed due to  lack of IO pins but the device usage was 88% which makes it not so certain (to me) that you could squeeze 19 hasher in the 22 k device.

While checking the numbers, i could verify that a hasher stage 'miningcore' would use 1157 LEs but this number excludes the sha256core submodule which seems a very important part to me . So you should recalculate your expectations with the number of 1925 LEs per hasher.

[nedbert9]

Good effort, Wondermine.

[wondermine]

Hm, how did you get the number of  Logic cells without having a qpf and qsf file?
Why do you design a control logic  with 288 IOs for a chip with only 167 usable IO pins (153 usable on the DE0 (including th pins for RAM etc.).

I tried to test compile the design for a cyclone IV with 30 kLE but fiting failed due to  lack of IO pins but the device usage was 88% which makes it not so certain (to me) that you could squeeze 19 hasher in the 22 k device.

While checking the numbers, i could verify that a hasher stage 'miningcore' would use 1157 LEs but this number excludes the sha256core submodule which seems a very important part to me . So you should recalculate your expectations with the number of 1925 LEs per hasher.

Correction: the .zip file comes with only a quickly thrown together sdc and no qpf, just vhdl.
-Edit-
I can admit a mistake, you're right, with zero register duplication, no optimization, no resource sharing, etc, the core takes up 1925.  But let me be very clear: with optimizations that size goes down significantly, I've shut off all optimization in order to preserve logic that would otherwise be synthesized away.  To think that it won't use sharing with all of the XOR, AND, and + repetitions is absurd.
Apparently, however, I need to revamp my numbers, so I'll get something back to you on the core controller soon.
Also, in the design report the multiplexer restructure savings alone are 81 LEs, so 1925 -> 1844 for the current design.

In better news, I have my mining core shrunk from 768 -> 582 LEs as of today.

Interesting. Assuming your design can be ported from the Cyclone IV to the Stratix III, an EP3SL200 at 213MHz with 250 of your 800-LE cores would produce 416 Mhash/s. That would account exactly for the performance of the BitForce Single (rumored to be two EP3SL200 chips = 832 Mhash/s)...

Does it port? Yes.  I don't have experience with the Stratix III series, does it use the same architecture (or similar) to that of the Stratix IV? If so the logic count would be decreased (compiling this on my Stratix IV gave me better numbers than the ones I've quoted).  I haven't looked into the pricing on that unit but work will continue and if Altera devices become advantageous, then we'll use them.