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Author Topic: Why no asics through smaller fabless manufacturers?  (Read 3437 times)
Gomeler
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March 13, 2012, 11:59:33 PM
 #1

Curious why, with a number of FPGA builders cropping up, there has been no mention of someone crowd sourcing funds for a run of ASICs on some of the cheaper processes.

A quick search pulled these guys up -> http://www.easic.com/low-cost-power-fpga-nre-asic-90nm-easic-nextreme/easic-nextreme-overview/

90nm is old tech which should translate to cheap and I would imagine we'd still see decent efficiency out of a chip.

There are a number of fabless manufacturers that sell portions of wafers that would let us avoid the immense outlay for an entire wafer and more importantly the masks.

This post of course has zero research behind it but with what I've seen on the FPGA threads there would be demand for a cheaper product that sat somewhere in the fpga range for power consumption and the GPU range for performance.

Thoughts? Anyone research this and find it unviable?

edit: I've seen a few threads with the same topic and everyone says "it costs a few million dollars for a run." easic's selling point is low costs per run. An article on their 45nm process quoted 20-100k for a run. Of course this is practically worthless without any information on the chip manufactured but keep in mind easic is making a business out of undercutting the bigger fabs.

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DeepBit
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March 14, 2012, 12:59:30 AM
 #2

eASIC offers 45 chips for $45 000. Such small quantities are possible because they are using ion-beam for vias layer configuration. Real mask-based layers will require tens of thousands units to be competitive.

Also, you need to design and place/route the chip and it's VERY expensive unless you have all the software, can do it and take the risk.

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March 14, 2012, 05:44:01 PM
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Any idea on the size of chip and manufacturing process for the 45 for $45k you are mentioning? If each chip is $1k but is able to compete on a MH/$ compared to GPUs then it could be a viable option. I guess all I'm getting at is that I feel like this avenue hasn't been truly explored asides from cursory glances and the regurgitation of "common" knowledge.

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March 14, 2012, 05:56:04 PM
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This "45 chips (45 nm chips) for 45 grand" deal
- was announced in 2010 and may no longer be available or more expensive now (2 years down the road)
- does NOT include the tool chain, most notably Synopsys DC (design compiler) and several tools by Magma

Nobody seems to know how much the Synopsys design compiler costs, but the word on the street is, typically you don't buy it, but rent it, and the rent for one year is in excess of 100 grand.

Thus, including the tool chain, you are looking at approximately $3000 or $4000 per chip, not $1000
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March 14, 2012, 06:01:12 PM
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Any idea on the size of chip and manufacturing process for the 45 for $45k you are mentioning? If each chip is $1k but is able to compete on a MH/$ compared to GPUs then it could be a viable option. I guess all I'm getting at is that I feel like this avenue hasn't been truly explored asides from cursory glances and the regurgitation of "common" knowledge.

It won't.  Also remember the price quoted is simply the "build cost" of just the chip.  You got the balance of the system and the tens of thousands of dollars (if not hundreds of thousands) in NRE designing the chip.  This isn't something like Visual Studio.  The software tends to be six figures and laying out an ASIC takes some qualified engineers months.  So figure 3 or 4 engineers on salary at $80K ea for 6-12 months plus software running $50K to $100K more plus likely some outside consultation or IP licensing for routine elements.

Solutions like eASIC are designed for rapid prototyping.

Say you simulate a chip of x millions of gates on 45nm process can get 600 MH/s and in bulk will be <$100 per chip.  Compared to existing solutions there is obviously a lot of potential profit but also a lot of risk.  Now instead of sinking $2M+ into the venture you could hedge your risk by taking your design, some seed capital (maybe $200K) and 6 months.  Once you got a functional design, you have eASIC custom cut you a couple dozen chips at $1K+ each.  Now the chip is $1K so you are talking $2,500+ for something comparable to BFL Single.  Obviously no market for that.

However the point isn't to sell the 4 dozen or so chips.  The point is you now have actual silicon in your hands.  Not an FPGA, not an sASIC, not a simulation, the actual silicon.  That is very valuable. You can build rigs out of them, test them, try different densities, see how far you can push the clocks, measure wattage, adjust cooling, burn them in, find bugs, perfect PCB designs, etc.  All the things that make investors scared you can get behind you.  You can show the chip works, it has a performance of X MH/s on Y watts and will cost $Z.

Then when you have a final perfect, tested design (not just chip but entire product) IN HAND you can go to the investors and say "see this works" and we can build this quad chip 3 GH/s system for $500 in bulk and likely sell it for a 300% markup.  We just need $2.8 million for the mask and run of first 2000 chips.  It is a lot less scary to drop something like $2.8 million if you have a product working in hand.
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March 15, 2012, 01:15:45 AM
 #6

This "45 chips (45 nm chips) for 45 grand" deal
- was announced in 2010 and may no longer be available or more expensive now (2 years down the road)
- does NOT include the tool chain, most notably Synopsys DC (design compiler) and several tools by Magma
Thus, including the tool chain, you are looking at approximately $3000 or $4000 per chip, not $1000
They had another offer with chip design software and manufacturing of 10 chips included in the price.

As for the NRE and mass production: this won't be ever profitable with less than q3000.
D&T guessed correctly about the design and layout for $200k at serious company (and there is still almost no warranty against failure).

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March 18, 2012, 11:24:40 AM
 #7

A realistic low cost asic would be something like 180nm and at least 9 wafers. (Much of those machines process 3x3 wafers)
This would result in something like couple of hundred to a few thousand chips.

Add to this packaging and testing.
That would be a custom asic, so it would still have tremendous benefit over fpgas and sasics, even with a large feature size.
None of those "compromises" will yield anything more cost effective for mining imo.

There is a reason why there is no fabless processor company utilizing sasics (or any of those things in between)
As you can see there isn't really a "low volume" segment once you realize that chips are made out of wafers, you add huge costs once placing different chips on a single wafer since the masks have to be changed and aligned each time.

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March 18, 2012, 12:09:52 PM
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A realistic low cost asic would be something like 180nm and at least 9 wafers. (Much of those machines process 3x3 wafers)
This would result in something like couple of hundred to a few thousand chips.

Add to this packaging and testing.
That would be a custom asic, so it would still have tremendous benefit over fpgas and sasics, even with a large feature size.
None of those "compromises" will yield anything more cost effective for mining imo.

There is a reason why there is no fabless processor company utilizing sasics (or any of those things in between)
As you can see there isn't really a "low volume" segment once you realize that chips are made out of wafers, you add huge costs once placing different chips on a single wafer since the masks have to be changed and aligned each time.
180 is massive, and my understanding is that ArtForz's farm was built on 130nm and is mostly obsolete now. (No faster than current FPGAs). Sorry, incorrect info.

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March 18, 2012, 12:14:21 PM
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180 is massive, and my understanding is that ArtForz's farm was built on 130nm and is mostly obsolete now. (No faster than current FPGAs).
It was rather 320 nm, but anyway 180 may be too big.

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March 18, 2012, 12:15:57 PM
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180 is massive, and my understanding is that ArtForz's farm was built on 130nm and is mostly obsolete now. (No faster than current FPGAs).
It was rather 320 nm, but anyway 180 may be too big.
Oops, my bad sorry.

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March 18, 2012, 01:03:23 PM
 #11

You cannot really compare fpgas & cell cell asic feature size and custom asics.
The logic alone for example. In a fpga or cell design you have a standard buffer element plus sram or mask rom.
With a custom you would only need a buffer element were you actually store a value the rest would be composed at the transistor/metal level.

That alone can be an order of magnitude more efficient, add to this a much higher clock rate and even asynchronous logic in most cases. Many existing fabless semiconductor companies offer solutions to incorporate custom designs in their solution and even provide the software for free, what would be needed is the quantity to fill a whole batch of wafers.

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March 18, 2012, 03:11:17 PM
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You cannot really compare fpgas & cell cell asic feature size and custom asics.
The logic alone for example. In a fpga or cell design you have a standard buffer element plus sram or mask rom.
With a custom you would only need a buffer element were you actually store a value the rest would be composed at the transistor/metal level.

That alone can be an order of magnitude more efficient, add to this a much higher clock rate and even asynchronous logic in most cases. Many existing fabless semiconductor companies offer solutions to incorporate custom designs in their solution and even provide the software for free, what would be needed is the quantity to fill a whole batch of wafers.

>and even provide the software for free

I've not seen that recently.
The multi-project wafer houses that I have looked at recently do not provide the tool chain and just run your wafer, or provide only PART of the tool chain (the back end, i.e. physical part).

For instance, in the flowchart on their site, eAsic specifically refers to the Synopsys design compiler being required (and no, they will not provide it for free, dream on).

If you have seen that somewhere, please point me to it.

20 years ago, different story. I helped someone with a standard cell ASIC (on 2um technology or whatever it was back then) at a standard cell house in Munich. The design software ran on Sun workstations and you would sit onsite and enter your design. I don't recall the name of the company but it was something like E2S or E2 or something.
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March 18, 2012, 03:53:48 PM
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I'm sorry I was under the impression chuck moores okad was shipped with colorforth. I researched it an it is not.
I followed them and what they are doing with their GA144, I long hoped it could be used for mining but the architecture is just too different (18 bit no hardware shift instruction), I said this because greenarrays advertised in their paper their processors can be built into custom design and they would ship the tools to do it.

There is some rumor that chuck planned to release his life work to the public domain at some point, I thought that was already here... since the chip is available for sale. well dream on  Wink

But that issue pretty much answered the question: Its the (again  Angry) the software.
I propose one could arrive at something practical using Magic VLSI.

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March 18, 2012, 11:52:41 PM
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In theory there is a complete digital design flow

http://opencircuitdesign.com/verilog/index.html

but following the links  there is on the website  for the cell library a warning that the library isn't nean't for producing Chips rather that benchmarking VLSI design flows. Producing Chips would be still possible but requiere more man month and fab runs.
15 years ago there was a open Source Gate Array System 'Ocean' for Sea of Gates Type array but this approach seems not very common these days.

Chuck Moors Okad seems to be a quite spartanic Software (only a few 100 Lines of code), arranging cells and routing the connections between the terminals. Just for laying out Forth Engines Cheesy

On opencores there is/was an fundraising for an open source asic, maybe someone could ask them for incorporating a 'special' Bitcoin mining unit Cheesy
One Idea i had was  modifiing the multiplication unit to doing the sha additions in one cycle, but i am not sure if its possible.
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March 19, 2012, 10:45:03 AM
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What about clusters like these:

http://www.dinigroup.com/new/DNBFC_S12_12_Cluster.html

http://www.dinigroup.com/new/DN2076k10.html


How much hashing power would come out of them and how much does stuff like this cost?
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March 19, 2012, 11:23:43 AM
 #16

Very underpowered and expensive. Won't work.

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