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Author Topic: Cyclone V now shipping!  (Read 12941 times)
Dexter770221
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March 30, 2012, 04:37:12 PM
 #1

I've just found this news in my email.
239$ for 150k LUTs part. Looks VERY promissing.
http://www.buyaltera.com/scripts/partsearch.dll/multisearch?site=ALTERA&lang=EN&keywords=5CE+A7+FPGA+IC
Currently out of stock...
Altera always have been a little bit expensive than Xillinx, so Artix7 200k may be with same or little lower price. This is gona be madness Wink

makomk:
Considering your 27.5 MH/s what is your estimation on this? 2x200MH/s?

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Gomeler
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March 30, 2012, 05:00:24 PM
 #2

So, slightly higher per LUT but it should have lower power consumption? I wonder if we'll see a clockspeed bump with the shrink from 40nm(?) to 28nm. Hopefully the new FPGAs will drop the MH/$ costs for FPGAs so I can start mixing these in to the GPU farm.

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March 30, 2012, 05:31:35 PM
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So, slightly higher per LUT but it should have lower power consumption? I wonder if we'll see a clockspeed bump with the shrink from 40nm(?) to 28nm. Hopefully the new FPGAs will drop the MH/$ costs for FPGAs so I can start mixing these in to the GPU farm.
Cyclone IV 115k LUTs is priced at 315$. So, this is much cheaper per LUT! Speed bump should be quiet significant becuse CIV are made at 65nm.

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March 31, 2012, 12:44:15 AM
 #4

Altera always have been a little bit expensive than Xillinx, so Artix7 200k may be with same or little lower price. This is gona be madness Wink

Artix 7 should be cheaper than Cyclone V, because Xilinx claims Artix 7 matches its predecessor's performance (Spartan 6) but sells at "35% its cost and is twice more energy efficient" (can't remember where I obtained this info, I just jotted it down a while back). That said, please do keep us informed about performance numbers you may achieve...
Dexter770221
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March 31, 2012, 09:05:33 AM
 #5

Artix 7 should be cheaper than Cyclone V, because Xilinx claims Artix 7 matches its predecessor's performance (Spartan 6) but sells at "35% its cost and is twice more energy efficient" (can't remember where I obtained this info, I just jotted it down a while back). That said, please do keep us informed about performance numbers you may achieve...

Not exactly as you quoted.
http://www.xilinx.com/products/silicon-devices/fpga/artix-7/index.htm
"... and offers over two times the capacity, 30% higher performance, 50% lower power consumption -- and logic up to 350K logic cell density at lower price points than Spartan®-6 FPGAs." 

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March 31, 2012, 10:35:24 AM
 #6

What kind of mh/s?
Dexter770221
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March 31, 2012, 11:04:53 AM
 #7

makomk achieved 27.7MH/s from CycloneIV 22k part. My quess is that is 220MHz core rolled 8 times. Fully unrolled core fits to 75k Cyclone. That gives two cores on 150k part and propably at 300MHz (28nm vs. 60nm), so 600MH/s may be possible...

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March 31, 2012, 01:46:23 PM
 #8

makomk achieved 27.7MH/s from CycloneIV 22k part. My quess is that is 220MHz core rolled 8 times. Fully unrolled core fits to 75k Cyclone. That gives two cores on 150k part and propably at 300MHz (28nm vs. 60nm), so 600MH/s may be possible...
Don't forget that eldentyrell was able to squeeze 3 unrolled cores onto a 150k part, although currently not getting a huge difference in speed (might later though, after some optimizations). Is there a 200k LUT part available? Might be able to fit 4 cores on it for 2 bitcoin hashing stages, instead of an odd 1.5 stages.

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March 31, 2012, 02:15:40 PM
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Don't forget that eldentyrell was able to squeeze 3 unrolled cores onto a 150k part

3 unrolled cores? afaik 3 cores with 0.5hash per cycle

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Dexter770221
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March 31, 2012, 02:30:02 PM
 #10

Spartan6 differs from CycloneIV. In first one only half of "slices" have carry chain logic that is very important in implementing adders. In Altera products every LUT have carry chain. Thats why you can put fully unrolled core to Cyclone 75k part and you need 150k part from Xillinx to do the same. Artix7 will have carry chains in every LUT, but ALM in CycloneV will have a LUT and an adder. It's almost impossible to direct compare this products when comes to predictions. Either way >2MH/$ from FPGA's is comming Wink

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March 31, 2012, 03:19:50 PM
 #11

Don't forget that eldentyrell was able to squeeze 3 unrolled cores onto a 150k part

3 unrolled cores? afaik 3 cores with 0.5hash per cycle
Yes, that's what I meant, but it's better than 2 cores with 0.5 hash per cycle.

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April 01, 2012, 12:12:20 AM
 #12

Either way >2MH/$ from FPGA's is comming Wink

How much and when can I get it?  Grin
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April 01, 2012, 03:03:41 AM
 #13

Don't forget that eldentyrell was able to squeeze 3 unrolled cores onto a 150k part

3 unrolled cores? afaik 3 cores with 0.5hash per cycle
Yes, that's what I meant, but it's better than 2 cores with 0.5 hash per cycle.
afaik other Spartan6LX150 miners have 1core with 1 hash per cycle
only eldentyrell has 3core with 0.5hash per cycle

yes its true 1.5 is better then 1,
i am sure there are more people trying to workout this nice 3core solution, i think its only a matter of time Wink

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Jason
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April 05, 2012, 03:11:32 AM
 #14

Thats why you can put fully unrolled core to Cyclone 75k part and you need 150k part from Xillinx to do the same.

Got a reference for this please?  I have not seen any publicly available HDL code for the Cyclone IV that needs fewer than about 100K LEs (fully unrolled).  This includes the code on fpgaminer's github (which includes some of Makomk's work) as well as Ztex's code.

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April 05, 2012, 05:19:34 AM
 #15

Quote
Got a reference for this please?  I have not seen any publicly available HDL code for the Cyclone IV that needs fewer than about 100K LEs (fully unrolled).  This includes the code on fpgaminer's github (which includes some of Makomk's work) as well as Ztex's code.
The makomk based code fits into ~80K-90K LEs unrolled, if I recall correctly. Though it has been awhile since I've compiled that code, so it might be less Smiley

Dexter770221
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April 05, 2012, 08:28:09 AM
 #16

Thats why you can put fully unrolled core to Cyclone 75k part and you need 150k part from Xillinx to do the same.

Got a reference for this please?  I have not seen any publicly available HDL code for the Cyclone IV that needs fewer than about 100K LEs (fully unrolled).  This includes the code on fpgaminer's github (which includes some of Makomk's work) as well as Ztex's code.

https://bitcointalk.org/index.php?topic=9047.msg446363#msg446363

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April 05, 2012, 02:42:21 PM
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Thanks for the reference.  Unfortunately, the URL to Makomk's code in the message you referenced does not exist, though perhaps his code is reflected by the DE2-115-makomk-mod branch of fpgaminer's code.  I just compiled that code with LOOP_LOG2 set to 0 and found that it compiles to 77,724 LEs/Fmax=109.84MHZ with the provided project settings, so probably 75K LEs can be achieved by optimizing for density (though this would reduce Fmax).  The only problem with the theory that the 5CEA7 (Cyclone V with 150K LEs) could challenge the LX150 is that even if you did manage to fit two fully unrolled loops into it (it's quite difficult to fit the last 10%), I would be surprised if you could get Fmax over 100MHZ due to the difficulty in efficiently routing such a design.  And in terms of MH/$, I just don't see it happening given the significantly lower cost of the LX150s ($160 vs. $240 for qty 1).  Depending on Altera's pricing on the 5CEA9 Cyclone V's (300K LEs), there may be more potential there (whenever they become available).

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April 05, 2012, 11:29:27 PM
 #18

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I would be surprised if you could get Fmax over 100MHZ due to the difficulty in efficiently routing such a design.
I wouldn't be surprised at all if a C5 with 150K LEs will do ~300MH/s (dual hasher design). In fact, I'd be disappointed if it didn't. Even a C4-150 is likely to do 200MH/s using a dual-core makomk core, a UART for communication, and removing the first three rounds. Cyclone chips have a lot better routing than Spartan-6. Immensely so. And it's a real shame, because the Spartan-6 has a lot better support for adders. Quartus also produces far more predictable results than ISE.

I would have preferred the Cyclone IV to have won the mining race against Spartan-6, honestly, but it was just too expensive. On the other hand, as frustrating as battling ISE is, there's always some amount of glory in winning battles against it Tongue

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April 06, 2012, 04:13:15 AM
 #19

I'm a bit puzzled by how you come up with 300MH/s.  Makomk's variation with about 78K LEs has an Fmax around 110MHz on the C4.  Squeezing two of these onto a C5 is going to be tough, and I don't see how you could do it without compromising the routing.  I suppose the 28nm fabric would mitigate that somewhat, but it seems a big stretch to get the Fmax all the way up to 150MHz.  The 60nm C4 hasn't proven to be much faster than the 90nm C2 based on my limited experimentation compiling LOOP_LOG2=1 designs for both FPGAs, although I did notice a significant reduction in power usage with the C4.

I guess it would be easy enough to download the latest version of Quartus to see what's possible on the C5.  Has anyone else tried this already?

As for ISE, it's the reason my company recently switched from Xilinx to Altera products for their high speed networking products.

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Dexter770221
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April 06, 2012, 08:25:44 AM
 #20

CycloneV ALMs have different structure than Cyclone IV. In one ALM you have four 4-input LUT + two 1 bit adders (with dedicated fast carry chains). So theoretically should be possible to put one stage into 160 ALMs (if I'm calculating right). 160*128=20480 ALMs for one fully unrolled core. 5CEA7 have over 56k ALMs, thats enough for two cores + some other logic for reciving, transmitting and distribuing work.

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Changing one PCB with screwdriver and you have brand new miner in hand... Plug&Play, scalable from one module to thousands.
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