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Author Topic: BitFury 110GH/s per rack?  (Read 10079 times)
arklan
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May 22, 2012, 11:12:52 PM
 #41

My point was, that 8 x 32 is not 240. It is 256.
If you can fit this in only 240 slices, then maybe 16 x 15 is a better geometry, since 16 x 15 really is 240.
Or am I missing the point here?

42? (i have nothing useful to say... sorry.)
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May 23, 2012, 01:11:26 AM
 #42

Or am I missing the point here?
Could it be related to the fact that a Bitcoin hash only needs 61 rounds instead of 64?

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May 23, 2012, 01:17:24 AM
 #43

Or am I missing the point here?
Could it be related to the fact that a Bitcoin hash only needs 61 rounds instead of 64?

No. Completely unrelated.

A guy or gal named Valery just responded to a personal email of mine with the clarification that they are indeed talking about 8 x 30 slices,
the same number a count on their screen shot comes up with.
In other words, 8 x 32 was a typo, which they have corrected on their website by now.
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May 23, 2012, 03:10:12 AM
 #44

I find it amusing people are comparing a non released product to something that is already operating and outputting real world numbers.

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May 23, 2012, 06:56:20 AM
 #45

On their website, they state:
Then after choosing serial round design it was very challenging to fit it exactly into 240 slices (8 x 32 area). As you see in snapshot image on the left, magenta color shows exactly two SHA256 rounds location. These double-SHA256 with round and round expanders and additional control logic fits into 240 slices. This took another month of development. Fitting in 240 slices was important to obtain good fill of XC6SLX150 right part.

I hate to break the news, but 8 x 32 is not 240. It is 256. At least, where I grew up.  Roll Eyes

So, what did they really do? Fit two rounds of SHA-256 into 240 slices, including control logic? I find that hard to believe.
Or fit two rounds of SHA-256 into 256 slices - I find that slightly easier to believe, but it still would be a major achievement.

i believe because we did just exactly the same.  2X 64cycle SHA256 core in 8X32 area, include control logic,  timing report is much over 300MHz.
the coding work is easy(maybe less than 50 lines.) but write the UCF files used month of time, and still have some small bugs now.  Smiley

My point was, that 8 x 32 is not 240. It is 256.
If you can fit this in only 240 slices, then maybe 16 x 15 is a better geometry, since 16 x 15 really is 240.
Or am I missing the point here?

i think it's really not important to a accurate number. our cores are using 256 slices. but only 64 clocks.

Or am I missing the point here?
Could it be related to the fact that a Bitcoin hash only needs 61 rounds instead of 64?

by special optimization on the arithmetic and setup pre-processors (certainly, inside the FPGA), it can reduce 3-4 calculate rounds.

I find it amusing people are comparing a non released product to something that is already operating and outputting real world numbers.

i think it's very close to us.

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May 27, 2012, 08:55:13 PM
 #46

Wow - someone has out-eldentyrelled eldentyrell...
That's what I thought as well when I saw this...

Hey, at least I get to share with zhoutong the dubious honor of having had my name verbified by the forum users.  I guess that's something! Wink

Does anyone know if bitfury's design stores the SHA-256 constants in BRAMs or has them spread over through the SLICEs?

Just guessing, but he probably daisy-chains the hashers in each clock region, runs them one step out-of-phase with each other, and has a single bram feed them k-values which get passed along from one hasher to the next, bucket-brigade style.  My very first design -- which was bit-serial (really bad idea!) -- worked that way.

There's actually several possibilities - one possibility that bitstream reads Device DNA code (it's serial number),

The DNA register is just a shift register; it's trivial to swap it out for an SRL32 in fpga_editor.

By the way, these guys have documented the bitstream format and made tools that turn .bit files back into .ncd files -- even (completely illegible) .v files in some cases.

It is bad that chip manufacturer implemented AES only, because if they would implement in silicon some public-private key infrastructure with Xilinx certificate - it would be much simpler.

I don't think Xilinx wants the liability that comes with being a certificate authority -- especially one whose certificates can't be revoked because they're burned into millions of dollars worth of silicon.  You can bootstrap similar schemes yourself on Virtex-6 and above; see section 6 of this paper.

Even with e-fuse it is less protection compared to SRAM + battery for AES key.

I wouldn't trust them if I were you.  It's completely trivial to extract the AES key from Xilinx devices, even Spartan-6.  Even battery-backed ram.  Only one power-on is required, and the equipment isn't expensive (if you rent it it's downright cheap).  They didn't fix this problem until Virtex-6.

About remote activation - it is pretty possible thing.

Quite prescient of you -- stay tuned.  But I'm not sure how well this would work for you -- with a highly-rolled design it's easy for an attacker to tell the difference between countermeasure circuits and the actual hashers -- just look for the pattern and chop out anything irregular.  Once you've got it down to a few hundred slices it's easy to figure out where the inputs and outputs are and what they mean. Replicate that block, stitch it back together and the game's over.

On the other hand, you guys make your own hardware -- that's a big advantage when it comes to anti-piracy measures.  You might be better off looking into ways to leverage that, like a tamper-proof housing around the spartan that erases the bitstream if breached and extra circuits to thwart power-analysis attacks.  People are also less likely to try to reverse engineer your work if they have to take apart and possibly damage a box they've paid $100,000 for!

The printing press heralded the end of the Dark Ages and made the Enlightenment possible, but it took another three centuries before any country managed to put freedom of the press beyond the reach of legislators.  So it may take a while before cryptocurrencies are free of the AML-NSA-KYC surveillance plague.
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May 28, 2012, 05:53:52 AM
 #47

Hey, at least I get to share with zhoutong the dubious honor of having had my name verbified by the forum users.  I guess that's something! Wink

So eldentyrell eldentyrell'ed existing Spartan 6 bitstreams, then bitfury eldentyrell'ed eldentyrell, and now BFL is trying to eldentyrell bitfury.

I simply don't have enough popcorn for this.

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May 28, 2012, 06:04:59 AM
 #48

ok, yea... that got some laughs out of me, d3.
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May 28, 2012, 06:30:06 AM
 #49

I don't think these announcements in close succession are a coincidence.

Seeing that EldenTyrell is planning to sell his 260 MH/s bitstream starting June 1st, Bitfury tried to preempt these sales by disclosing their own 300 MH/s bitstream, which has a better price/performance ratio than BFL's Single, at about half the power draw. Of course, BFL doesn't want Single sales to drop off by 95%, hence they pre-announce their ASIC, and thus ensure that sales of Lancelot, Bitfury and Eldentyrell's bitstream will be zero or close to zero. But such a pre-announcement of a better product can have a devastating side effect on your OWN product sales as well, which has bankrupted more than a few companies. For the baby boomers among us, let me just mention Osborne. Enter the buy-back guarantee. The buy-back guarantee ensures that BFL's sales will be unaffected by the pre-announcement - nobody will cancel existing orders and nobody will shy away from new orders.

Brilliantly played, BFL.
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May 28, 2012, 06:37:15 AM
 #50

I don't think these announcements in close succession are a coincidence.

Seeing that EldenTyrell is planning to sell his 260 MH/s bitstream starting June 1st, Bitfury tried to preempt these sales by disclosing their own 300 MH/s bitstream, which has a better price/performance ratio than BFL's Single, at about half the power draw. Of course, BFL doesn't want Single sales to drop off by 95%, hence they pre-announce their ASIC, and thus ensure that sales of Lancelot, Bitfury and Eldentyrell's bitstream will be zero or close to zero. But such a pre-announcement of a better product can have a devastating side effect on your OWN product sales as well, which has bankrupted more than a few companies. For the baby boomers among us, let me just mention Osborne. Enter the buy-back guarantee. The buy-back guarantee ensures that BFL's sales will be unaffected by the pre-announcement - nobody will cancel existing orders and nobody will shy away from new orders.

Brilliantly played, BFL.

Yeah except DMC could very well be the largest buyer of miner hardware, and if I don't like what BFL now is doing, I won't buy their hardware in the future no matter how cheap it is, and would do business with Bitfury and Eldentyrell instead (who, really, should be combining forces right about now).

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May 28, 2012, 08:21:20 AM
 #51

Yeah except DMC could very well be the largest buyer of miner hardware, and if I don't like what BFL now is doing, I won't buy their hardware in the future no matter how cheap it is, and would do business with Bitfury and Eldentyrell instead (who, really, should be combining forces right about now).

Bring it on Cheesy

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May 28, 2012, 01:39:26 PM
 #52

I don't think these announcements in close succession are a coincidence.

Seeing that EldenTyrell is planning to sell his 260 MH/s bitstream starting June 1st, Bitfury tried to preempt these sales by disclosing their own 300 MH/s bitstream, which has a better price/performance ratio than BFL's Single, at about half the power draw. Of course, BFL doesn't want Single sales to drop off by 95%, hence they pre-announce their ASIC, and thus ensure that sales of Lancelot, Bitfury and Eldentyrell's bitstream will be zero or close to zero. But such a pre-announcement of a better product can have a devastating side effect on your OWN product sales as well, which has bankrupted more than a few companies. For the baby boomers among us, let me just mention Osborne. Enter the buy-back guarantee. The buy-back guarantee ensures that BFL's sales will be unaffected by the pre-announcement - nobody will cancel existing orders and nobody will shy away from new orders.

Brilliantly played, BFL.

the only osbourne i know is norman (aka the green goblin), and a google for "osbourne company, -ozzy, -kelly, -sharon" fails to return anything. care to link?

also, BFL's pay up front policy was always a genius (if somewhat controversial) way to ensure enough bankroll to ramp up production while guarding against competition.

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May 28, 2012, 01:52:24 PM
 #53

the only osbourne i know is norman (aka the green goblin), and a google for "osbourne company, -ozzy, -kelly, -sharon" fails to return anything. care to link?

http://en.wikipedia.org/wiki/Osborne_Computer_Corporation
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May 28, 2012, 02:06:42 PM
 #54

the only osbourne i know is norman (aka the green goblin), and a google for "osbourne company, -ozzy, -kelly, -sharon" fails to return anything. care to link?

http://en.wikipedia.org/wiki/Osborne_Computer_Corporation

interesting read, thanks

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May 28, 2012, 03:46:54 PM
 #55

Does anyone know if bitfury's design stores the SHA-256 constants in BRAMs or has them spread over through the SLICEs?

Just guessing, but he probably daisy-chains the hashers in each clock region, runs them one step out-of-phase with each other, and has a single bram feed them k-values which get passed along from one hasher to the next, bucket-brigade style.  My very first design -- which was bit-serial (really bad idea!) -- worked that way.

CONFIRM. Exactly how this is done... Why to install multiple K RAM, if you can install only few one per whole chip ? ;-)

There's actually several possibilities - one possibility that bitstream reads Device DNA code (it's serial number),

The DNA register is just a shift register; it's trivial to swap it out for an SRL32 in fpga_editor.

I've thought that it is different to convert .bit to .ncd .... But as you given me following links it seems to be trivial...

By the way, these guys have documented the bitstream format and made tools that turn .bit files back into .ncd files -- even (completely illegible) .v files in some cases.

-1 for Xilinx... it means that their bitstream non-disclosure protection basically make burden on normal developers, but not defies hackers / ip thieves, because they would have time and money to invest into reverse-engineering tools.

It is bad that chip manufacturer implemented AES only, because if they would implement in silicon some public-private key infrastructure with Xilinx certificate - it would be much simpler.

I don't think Xilinx wants the liability that comes with being a certificate authority -- especially one whose certificates can't be revoked because they're burned into millions of dollars worth of silicon.  You can bootstrap similar schemes yourself on Virtex-6 and above; see section 6 of this paper.

Just downloaded it... But if .bit -> .ncd could be converted - it will be not difficult to decode keys from chip. OR - EXTREMELY complex self-modifying bitstream should be made for protection alone... So costs would be not justified for this SHA256 thing protection alone... I've implemented some time ago meta-translators for x86 code protection, generating morphed code & executable difficult for analysis, and with FPGA it would be even more complex.

Even with e-fuse it is less protection compared to SRAM + battery for AES key.

I wouldn't trust them if I were you.  It's completely trivial to extract the AES key from Xilinx devices, even Spartan-6.  Even battery-backed ram.  Only one power-on is required, and the equipment isn't expensive (if you rent it it's downright cheap).  They didn't fix this problem until Virtex-6.

So in -7 series they will make logic that consumes _same_ power not depending on their internal key, so correlation will not be possible ? Have they at least aware of such bug ?

About remote activation - it is pretty possible thing.

Quite prescient of you -- stay tuned.  But I'm not sure how well this would work for you -- with a highly-rolled design it's easy for an attacker to tell the difference between countermeasure circuits and the actual hashers -- just look for the pattern and chop out anything irregular.  Once you've got it down to a few hundred slices it's easy to figure out where the inputs and outputs are and what they mean. Replicate that block, stitch it back together and the game's over.

On the other hand, you guys make your own hardware -- that's a big advantage when it comes to anti-piracy measures.  You might be better off looking into ways to leverage that, like a tamper-proof housing around the spartan that erases the bitstream if breached and extra circuits to thwart power-analysis attacks.  People are also less likely to try to reverse engineer your work if they have to take apart and possibly damage a box they've paid $100,000 for!
[/quote]

I'll wait for your release, anyway you have my question in your thread.... And I may reconsider initial licensing offer, as I still have no binding on that of course. As I still have about 200 Gh/s power, and if it would become 240 Gh/s - that would be nice benefit. And it is substantial benefit, as I can get board for say

$700 without VAT with 6 spartan6 on it - if it would be 1.8 Gh/s this means $0.38 per Mh/s
if it would be 2.2 Gh/s this means $0.32 per Mh/s.

So looking again on these numbers and having troubles with protection of bitstream, all of these devices can be "on hold" in some datacenter say in Iceland in name of their owners, but without ability to get them in hardware or get access without our consent/permission to equipment until IP released open-source. And open-source release I believe should be done at least for educational purposes, when we'll be ready to roll out best 28nm technology. Say this could be beneficial for DMC initiative. Also _existing_ hashing power (200 GH/s) can be good backing that equipment would be actually deployed, as my investors trust me with this.

So the coupon for 1 Mh/s with say 1 year hardware redemption possibility if you get enough for single board + shipment can be sold for about $0.60 + cost of equipment maintenance, insurance, etc - that would be fair price. And seems to be more fair play than "perpetual bonds" without significant backing, where bond issuer can go defunct half the road etc.
And also looking @ GLBSE it seems to be very risky, I suppose that some legal framework needed for this, to protect rights of buyers. Just putting reputation against such venture would be not enough I think. As investing into mining not with 4-6 month break even point would scare off investors if they would feel that fighting for their rights could cost more and without returning their assets than invested funds.

One of the ways could be - implementing specialized legal-based framework for hashing power trading. For example domain names are sold - sold legally and without any problems... And people not worry owning domain name worth say $10'000'000 etc. The same should be with equipment probably for mining, as this could help dramatically to secure investments into IP alone. Into ASIC for example as well. As when it would come to invest say $5 M into ASIC production, and there will be right engineers to proceed - it would be still great problem that "good fellow who organized all of that" would not just take part of these money and run away.


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May 28, 2012, 04:00:21 PM
 #56

I'll wait for your release, anyway you have my question in your thread.... And I may reconsider initial licensing offer, as I still have no binding on that of course. As I still have about 200 Gh/s power, and if it would become 240 Gh/s - that would be nice benefit. And it is substantial benefit, as I can get board for say

$700 without VAT with 6 spartan6 on it - if it would be 1.8 Gh/s this means $0.38 per Mh/s
if it would be 2.2 Gh/s this means $0.32 per Mh/s.

Feel free to not disclose this, but what kind of volume are you going through that you're able to get a finished board with 6 LX150s on it for $700? I would have thought that even in large volume the S-6 LX150s would cost close to that.
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May 28, 2012, 04:02:15 PM
 #57

I'll wait for your release, anyway you have my question in your thread.... And I may reconsider initial licensing offer, as I still have no binding on that of course. As I still have about 200 Gh/s power, and if it would become 240 Gh/s - that would be nice benefit. And it is substantial benefit, as I can get board for say

$700 without VAT with 6 spartan6 on it - if it would be 1.8 Gh/s this means $0.38 per Mh/s
if it would be 2.2 Gh/s this means $0.32 per Mh/s.

Feel free to not disclose this, but what kind of volume are you going through that you're able to get a finished board with 6 LX150s on it for $700? I would have thought that even in large volume the S-6 LX150s would cost close to that.

No, in volume of 100s, a Spartan6-150 costs just barely more than $100. $110, $115, $120, something like that.
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May 28, 2012, 04:08:23 PM
 #58

I'll wait for your release, anyway you have my question in your thread.... And I may reconsider initial licensing offer, as I still have no binding on that of course. As I still have about 200 Gh/s power, and if it would become 240 Gh/s - that would be nice benefit. And it is substantial benefit, as I can get board for say

$700 without VAT with 6 spartan6 on it - if it would be 1.8 Gh/s this means $0.38 per Mh/s
if it would be 2.2 Gh/s this means $0.32 per Mh/s.

Feel free to not disclose this, but what kind of volume are you going through that you're able to get a finished board with 6 LX150s on it for $700? I would have thought that even in large volume the S-6 LX150s would cost close to that.

No, in volume of 100s, a Spartan6-150 justs just barely more than $100. $110, $115, $120, something like that.

That's what I mean, $700/6 = $117. That doesn't leave a lot of room for the board, other components and assembly. I was wondering how many FPGAs he's going through.
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May 28, 2012, 04:31:28 PM
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I'll wait for your release, anyway you have my question in your thread.... And I may reconsider initial licensing offer, as I still have no binding on that of course. As I still have about 200 Gh/s power, and if it would become 240 Gh/s - that would be nice benefit. And it is substantial benefit, as I can get board for say

$700 without VAT with 6 spartan6 on it - if it would be 1.8 Gh/s this means $0.38 per Mh/s
if it would be 2.2 Gh/s this means $0.32 per Mh/s.

Feel free to not disclose this, but what kind of volume are you going through that you're able to get a finished board with 6 LX150s on it for $700? I would have thought that even in large volume the S-6 LX150s would cost close to that.

I've already disclosed it, but I would not exactly tell that say Spartan has price $xxx because it is not the case with chip markets, as what basically cost there is not chip production, but NRE (R&D, masks, marketing etc) costs that Xilinx paid to make Spartan's rolling. And price for it will be falling with time.

But most important for Xilinx is not to make competition for their sales of Sparan's for other purpose - i.e. that will not buy it for $50 and sell for $100 to other contractors of them, who buy them at $100 level.

This is as ASIC vs FPGA design... FPGA is basically custom ASIC... do you think that its price is what silicon worth ? It's basically interest that FPGA vendor would like to get. I've told it already - that if FPGA vendor would like to - he can blow off with 28-nm say Virtex-7 sales for $50 that could be priced $10k on digikey any ASIC initiative here... And FPGA vendors more likely impose danger, as FPGAs are better suited for such calculations than say what GPU vendors manufacture...

This is what actually rises concerns about proof-of-work overall security. If you mention Scrypt - then - I can place about 4 to 6 hashers inside of Spartan and get blowing off speeds for that..... So it is even worse... As this makes edge for FPGA actually better than worse. As RAM accesses could be pipelined via multiple pipes............ getting bandwidthes that would not be available within usual computers/GPUs. Although I cannot parallelize single Scrypt, I can execute MULTIPLE calculations of different Scrypts - that's the point... Pipelining accesses to RAM...

What can really make benefits - is the both - modification of hashing algorithm and calculated hash, making ASICs obsolete, and highly-tuned FPGA modules, GPU modules and CPU modules more or less comparable. But that requires complex research indeed and probably not question of current day, and it should be performed by people not only who knows math in cryptography, but who also knows how hardware could be implemented etc. This not going to happen soon indeed as well.

And another weakness is ability to merge mining into pools... As this allows to manipulate hashing power against network...
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May 30, 2012, 04:01:58 AM
 #60

Quote
$700 without VAT with 6 spartan6 on it - if it would be 1.8 Gh/s this means $0.38 per Mh/s

Do want!

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