Leading SHA256 Solution Provider Acquires Venture Capital Funding

[eldentyrell]

I'm sorry, I know the silliness factor is already pretty high with the claimed 5600% improvement in efficiency:

… ~40x efficiency improvement for SHA256 hashing from 65nm FPGA to 130nm ASIC.

Spartans are 45nm FPGA, not 65nm.

So what? Do you know what node BFL used?

No, and I don't care.  They're claiming 5600% improvement over the current best MH/J, which is Spartan-6.  Spartan-6 is 45nm.

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[1715082806]

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[P4man]

If you had read the papers I linked, you would have seen how that kind of power efficiency is more than plausible with a 130nm asic, nevermind a 90 or 65nm one.

I honestly wouldnt have thought someone with your background would even need to see such papers to believe that though, so Im gonna assume you are just pretending.

[eldentyrell]

http://rijndael.ece.vt.edu/sha3/publications/DSD11SHA3.pdf

WTF?  What part of "not peer reviewed" do you not understand?  This is some powerpoint slide deck thrown together by a student.  About as academically credible as my press release.

http://filebox.vt.edu/users/xuguo/homepage/publications/CESCA_Seminar_SHA3.pdf

Right there on the front page almost in <blink> tags:

Our objective is to use the FPGA as a prototyping technology for the ASIC, rather than a direct technology target. Hence, dedicated FPGA optimizations are not used.

They didn't optimize the FPGA design at all.  Notice that their performance section only compares the ASIC implementations against each other (which was the whole point of the paper), not against the FPGA implementation.

[sadpandatech]

If you had read the papers I linked, you would have seen how that kind of power efficiency is more than plausible with a 130nm asic, nevermind a 90 or 65nm one.

I honestly wouldnt have thought someone with your background would even need to see such papers to believe that though, so Im gonna assume you are just pretending.

I read those papers but could not find where almost 100% utilization of the chips they were using would provide such effciency. I saw the low mW usage listed for each participants section but no indication of the actual utilization of the silicon in those sections to indicate whether the MHz they were running at was maxed out, etc. And we have no clue at this point what Freq BFL will be running theirs at.

[eldentyrell]

...

If you had read the papers I linked...

Damn, dude, you expect me to read them in 9 minutes? (see timestamps above)  Anyways, please refer to the ginormous red text two posts back; it answers your concern.  I made it big and huge and glaring and red so you wouldn't miss it this time.

[MrTeal]

To be fair, the paper from Virginia Tech is also using 0.13 standard cell. If BFL isn't lying about the ASIC being full custom, there could be optimizations on the ASIC side as well.

[P4man]

Right there on the front page almost in <blink> tags:

Great, so you (mis)read the first paragraph,  now scroll down to the last page and see the power and performance results for the reference 130nm asic implementation.  

[P4man]

To be fair, the paper from Virginia Tech is also using 0.13 standard cell. If BFL isn't lying about the ASIC being full custom, there could be optimizations on the ASIC side as well.

Highly unlikely they used anything other than standard cell. But their published performance is completely believable for a 130nm standard cell implementation (particularly if its optimized for bitcoin only) and no one has said its 130nm, it could even be a smaller node.

Some skepticism regarding BFLs claims and in particular, the timetable is warranted, but its ridiculous to pretend these numbers are somehow completely impossible.

[P4man]

If you want to see what a 90nm asic could do:
http://www.cosic.esat.kuleuven.be/publications/article-1500.pdf
Table 3
5.5 Gbps @ 3.1mW

[MrTeal]

If you want to see what a 90nm asic could do:
http://www.cosic.esat.kuleuven.be/publications/article-1500.pdf
Table 3
5.5 Gbps @ 3.1mW

Would a core throughput of 5.5Gbps translate to a single through hashrate of 10MH/s, and a double SHA2 hashrate of ~5MH/s?

[rjk]

If you want to see what a 90nm asic could do:
http://www.cosic.esat.kuleuven.be/publications/article-1500.pdf
Table 3
5.5 Gbps @ 3.1mW

5.5 Gbps is at a core frequency of 735 Mhz, and the 3.1mW power number has this note by it: "The power consumption is estimated for the frequency of 100 MHz". Furthermore, all the numbers are synthesized. They say they plan to tape out all the different implementations for comparison, but I don't think that's actually been done yet.

[eldentyrell]

Right there on the front page almost in <blink> tags:

Great, so you (mis)read the first paragraph,  now scroll down to the last page and see the power and performance results for the reference 130nm asic implementation.  

Our objective is to use the FPGA as a prototyping technology for the ASIC, rather than a direct technology target. Hence, dedicated FPGA optimizations are not used.

[P4man]

Maybe if you render the entire paper in that same big red font you can actually read it and understand that the FPGA was used for prototyping and therefore FPGA specific optimizations where not used. Now read about the ASIC, will you?

Oh well, I guess you are just trolling. You can lead a horse a water...

[eldentyrell]

Maybe if you render the entire paper in that same big red font you can actually read it and understand that the FPGA was used for prototyping and therefore FPGA specific optimizations where not used. Now read about the ASIC, will you?

Our objective is to use the FPGA as a prototyping technology for the ASIC, rather than a direct technology target. Hence, dedicated FPGA optimizations are not used.

[P4man]

Still stuck on page 1 I see.
Here I was thinking you were smart.

Let me try big fonts.

BECAUSE THEIR GOAL IS BUILDING AN ASIC

WTF do you want them to optimize for an FPGA? Go read the ASIC results.

[eldentyrell]

WTF do you want them to optimize for an FPGA?

Oh, I dunno, maybe because you posted the paper in defense of this comment?

Its completely in line with academic papers and even a SHA256 research chip which promised ~40x efficiency improvement for SHA256 hashing from 65nm FPGA to 130nm ASIC.

BTW, I can post that paragraph from the first page again in blue if you like!

[P4man]

You realize they are different documents right?  If you had read my posts or read beyond page 1 of the paper you keep quoting, you might have noticed at the end it has actual performance and power numbers for the asic implementation. You can compare that to whatever  uber optimized fpga you want, so who the fuck cares about that quote of yours about what they did during prototyping. Their ASIC numbers are NOT relative to the FPGA prototype, those arent even published.

The other document, the powerpoint, is a head on comparison between FPGA and ASIC implementations.

But who cares, clearly you are not interested in reading or finding out what you dont want to know.

[galambo]

See this is the stage where all the geeks on the forum argue until they basically come up with a plausible design for BFL's products given their vaguely specified performance claims.

And, if BFL is a dishonest actor, they could use this information to continue being dishonest.

[dropt]

See this is the stage where all the geeks on the forum argue until they basically come up with a plausible design for BFL's products given their vaguely specified performance claims.

And, if BFL is a dishonest actor, they could use this information to continue being dishonest.

You're mem, aren't you?  +1 for the ignore list just in case.  Furthermore, these guys aren't geeks;  they're educated individuals.  You've obviously got nothing to add, it'd be my suggestion to shut-up and maybe you'll learn something.

[P4man]

If you want to see what a 90nm asic could do:
http://www.cosic.esat.kuleuven.be/publications/article-1500.pdf
Table 3
5.5 Gbps @ 3.1mW

5.5 Gbps is at a core frequency of 735 Mhz, and the 3.1mW power number has this note by it: "The power consumption is estimated for the frequency of 100 MHz". Furthermore, all the numbers are synthesized. They say they plan to tape out all the different implementations for comparison, but I don't think that's actually been done yet.

Sure, they are estimates  based on pre-layout synthesis, and afaik the 90nm chip hasnt been built, but at this point the same probably goes for the BFL chip, so its not an unfair comparison . The 130nm chip was build. In fact, you can request a free sample if you want.

ITs also worth pointing out these chips are not optimized for bitcoin, but general purpose sha2 hashers. The 130nm chip isnt even optimized for SHA2 the whole paper describes all the trade offs they made to get those 5 or whatever competing SHA3 algorithms implemented. Whatever you want to read in to the results, they are not the highest possible, most definitely not for bitcoin.