It is NOT just down to the number of gates........
Take for example the following:
XC5VLX110T = 17,280 slices
XC3S1600E 33,192 gates , 14,752 slices
A fully unrolled design fits in the XC5 ,but in the XC3 it utilizes >300% of the resources, re-rolling the algorithm produces stupidly small amounts of hashes <40MH/s
It is how the cells/slices are configured and the functionality they provide...
Sha256 is very "Rotation" and addition driven, so if your device has this logic built in, then a 32/64 bit adder unit is gonig to take up WAY less than if you implement it from 2 bit adders
Also this logic is flawed.....
Nope. Two rounds of bitcoin hashes = 132 clocks acording to this:http://www.actel.com/products/ip/search/detail.aspx?id=627
If I build a massively parallel design then I can actually recover 1 hash every cycle, after an initial startup of the flow through.
I researched this because I had seen someone selling 30 XC3S1600E@$10USD each, and I had a plan..........
I also know that 'Razorfishsl' has a large XC5VLX110T array for crypto research, (RF, for the record I think you are a twat,Rgrds. the legal action... I'm keeping the Hardcorefs account...)