Bitcoin Forum

Hi everyone. Our team has just started a project of mining ASIC design & production. We believe it will be both profitable for us and good for the Bitcoin community if we fully work it out.

It is widely believed that the NRE cost of ASIC is very high, while the margin cost of mass ASIC production is very low. However, we happen to be in China, where the NRE cost is much more reasonable (~150k$ for 130nm, ~500k$ for 65nm, furthermore much less if you do a 1/N mask) than most people thought. And we are going to take well advantage of that.

Our approach is incremental in all aspects. We will set several milestones and see what will happen if we achieve each of them. The report on each stage will be posted here.

In the design stage, including both the front-end and the back-end, we are going to fund ourselves. When we are finally ready to turn our design into real chips, we will seek investments, possibly both inside and outside the Bitcoin world. The first batch of our ASIC will not be an end, and we are going to renew our technology with the evolution of the hardware industry, so we are going to make this project a long-term one. However, this thread is not for investment asking, but merely for discussion and our status report.

Open discussions (feel free to add more!)

1. Self mining .vs. Selling hashes .vs. Selling hardware

2. Warnings, e.g. what are the typical causes to a failed ASIC manufacturing

3. Approaches to get enough funding for production

(To be extended)

Status reports

July 18
We have had our IC design company registered at Shenzhen, China. The name of our company is "bitfountain"

We also have signed the confidential contract with the IC manufacturer and got the process library necessary for correct DC synthesis.

July 29

Front-end work done. Preliminary specification given.

August 2

More optimization and trade-offs applied. MH/J improved and Watt/mm^2 reduced at the cost of some chip area increase.

August 11

The pictures of our IC layer are revealed.
http://img3.douban.com/view/photo/thumb/public/p1664468687.jpg
(Larger pictures: https://bitcointalk.org/index.php?topic=99497.msg1092138#msg1092138)

September 22
We are in the taping-out process with the foundry. The chip spec and interface made public.
https://bitcointalk.org/index.php?topic=91173.msg1211518#msg1211518

(To be extended)

I think that there is demand for an alternative to BFL because many (myself included) do not like their business practices. If you have a competitive product then I'm sure that somebody would be willing to act as a distributor / retailer to handle the shipping for you (and to earn some money).

+1.

You can sell gear and not have to deal with thousands of customers.

Which technology background has 'we'? Did you make a FPGA miner oder other project including bitstream, schematic and pcb Artwork for yourself. Did you make an ASIC before?

Ok.. so you announce in the custom hardware forum about a product that you may develop that nobody can buy. You instead state that you will mine on the hardware for yourselves and sell some of the hashing power.

Why would you even waste the time to post all this information here? Make a website, post to the mining sub-forum and/or marketplace->services and who cares where the hashes come from. We don't care that it costs $xxx,xxx dollars to manufacture your masks and the ROI when all you are selling is a commodity(hashes).

This is like selling bushels of wheat and telling me how much sun was needed, how much fertilizer was needed and how much gasoline was used to plant, tend and harvest. Just sell me the damn wheat.

Thanks for your reply. It's not a single-sided announcement from us. It's supposed to be a board asking for discussion. We have some plans ourselves but since we haven't got any real Bitcoin community in the physical real world, this forum is a precious place for us to get information.

Therefore we are kind of chatty and informal in this thread, and we share the information as long as it's not IP-related or business-secret-related. And thanks to the replies, we realize that we pre-maturely ruled out the possibility of selling chips. Though things are not as feasible as western countries in China to sell tangible products, it's still viable.

The custom hardware sub-forum seems indeed to be not he best place to put this thread in. If the mining section is more suitable. Could the moderator move it to there?

"We" the founders are three people at this moment. One of the partner has been working on the hardware section of a general purpose CPU design group. The other one has been working on the software section of a embedded-system-oriented CPU group but is heavily involved in the front-end of hardware design.

So we have the ASIC experience, but in different larger projects, and as smaller roles than, say, "they are made by just us".

The license and permission of selling products to either direct customers or retailers in China are a little more painful to get. But you are right, it should still be taken into account as a possibility. Thanks for your suggestion.

The Bitcoin community would welcome a competing ASIC option to BFL with open arms. If you need proof of this just check out the responses and orders going on in the Enterpoint thread for a product that barely even works. The openbitASIC discussion is another great example of people clamoring for another option. A company that does ASICs right is a company that will win loyal customers. I firmly believe people put up with BFL because the rewards currently outweigh the difficulties. Hell, I even considered purchasing a few Singles myself..

Otherwise, another mining company, regardless of how the hashes are generated, is just another mining company.

Indeed. It is always a better thing for other miners to see direct competition of mining device providers than indirect ones. We are not in a proper position to comment other ASIC vendors or producers though. :)

I would personally love to see a well documented Bitcoin-specific ASIC that is sold by reel (or in smaller quantities to hobbyists by a retailer). This way there could be many companies developing and offering products from "coffee-warmers" to 4U Terahash-class racks. ASIC performance would this way be available to all at a reasonable cost, and the manufacturer/owner of IPR would get a fair flow of income without the hassles of consumer relations and warranty.

Indeed. This saves most hassle dealing with end-users. We hope the whole Bitcoin economy will soon grow to a level allowing a well-developed chain of mining industry so that we could implement this idea. Thank you very much for your suggestion.

+100!

One step further though (or perhaps back, depending how you look at it) how about a rather generic SHA256 ASIC?  Put two of them nut-to-butt and there's 90% of your miner; put one into a cryptophone or whatever else uses hashing.  This would increase your market by a massive factor, and in doing so decrease your per-unit design cost and thereby price.

How small could one make a simple SHA256 chip?  If they can fit three complete unrolled engines on a single S6LX150, one can be crammed into a damn tiny bit of silicon real estate.

As a Chinese manufacturer, you'd also be uniquely placed to market PCBs, assembled boards, and even assembled BFL-style units at really competitive prices.  Initially though, at least to recoup the initial investment, I'd vote for a single generic SHA256 engine on a chip as the best answer.

Thanks for your advice. Our first generation will be customized for mining only (bitcoin-specific constants baked in, only information about nounces being passed out), but in the future we will make generic SHA256 ASICs if there's indeed much other use.

I guess your "put two of them nut-to-butt and there's 90% of your miner" means two hashing units. Because both "two hashing units in one chip" and "one hashing units, two rounds for a double SHA256" are much more technical viable than separating two hashing units into two chips then using outside circuits to make them communicate.


The technology of our first batch products will not be as good as, say, 45nm. Therefore, we believe they will be small, but not crazily small. :)

Update

We have had our IC design company registered at Shenzhen, China.

We also have signed the confidential contract with the IC manufacturer and got the process library necessary for correct DC synthesis.

I kinda chuckled when I read your name. I read a few pages in Lord of the Rings (魔戒) and they transliterated "hobbits" into 霍比特人 (huòbǐtèrén)

Anyways... fun times =)

By "my name", I guess you mean my forum id instead of our company name, because the latter is quite normal. My forum id is indeed kinda weird but shouldn't be read literally. It has been my nickname for many many years in the real world.

There's another alternate translation of "hobbits", that is 哈比人(hābǐrén). Both are transliterations. :)

I actually meant your business name because 泉 and 人 (while different phonemes) can sound similar in certain dialects. And of course 比特 from 霍比特人. I haven't seen that one, but it could have been used in a different translation.

Either way 音译 (transliteration) of names is such a pain in Chinese. Since more and more Chinese are becoming (slightly) proficient in English I imagine in time they will stop doing it and just use the actual English/German/French/whatever name. I remember taking my final test in Chinese and I heard the name 马拉多纳 (ma la duo na) which sounds like 'maladewanaw,' and it took me a few seconds to get it was Maradonna...  :D

Anyhow... *thread hijack over* sorry ;)

Update

Our RTL design, optimization and simulation are finished. We have some data to predict the specification of actual chips after they are manufactured.

Hashrate: 1.25GH/s per chip
Area: 17.5mm^2 per chip
Power Consumption: 13.3W

Note that they are calculated from the front-end design and not accurate enough. But of course the possible difference range won't be large. We will keep our updates.

13W at 17 square mm - seems like a significant mount of heat to deal with.

When I was a kid, I used to have a 25W soldering iron and it was melting solder perfectly well. :)

Well, directly decreasing both the voltage and the frequency will dramatically reduce the power consumption. But the hashing rate per wafer will also reduce. This statistics is basically a result of trying to drive the hashrate/area to the highest given our 130nm choice. We will fix the whole design in the earlier iteration of back-end, then we probably will get a better compromise.

So about 5 times better than current LX150 chips/bitstreams in terms of hash rate per watt, is that about right? And this is on 130nm? Are you able to guess how much improvement might be had with a straight die shrink?

Yeah, I was just saying that one of your challenges will be how to drain the heat out of the tiny chips.
Especially assuming that you'd probably want to have a single PCB with many of such chips working in parallel.

It's hard to give an accurate guess. But I believe that the power consumption is (way) proportional to total area if the circuit structure does not change. We haven't investigated die shrink from the foundry yet but currently anything beyond 130nm is also beyond our budget.

This kind of heat density is not very common. The hardware implementation of SHA-2 involves too many unavoidable registers, and they all flip frequently. Larger heat sinks will do the work, but they reduce the density of chips on a single PCB. Also we have clock-lowering and the voltage-lowering as the last resort.

Anyway this problem will definitely be tackled. Fortunately our first batch of chips will probably consumed by ourselves, so the requirements of PCB design will be lower than that of a full-fledged Rig design, and heat issues are more tolerable at this stage. Of course, making high-quality mining devices that's usable by retail buyers is another story, and more challenging.

Any specs or pinouts yet?

Don't forget to ask the analog side of your fab for the suggestions on the casing. If you use serial I/O then 8 pins should be plenty. And if you need only 8 pins you could use one of the many IC cases designed for power analog application with a screw-hole for the heatsink mounting. The PCB will be an afterthought distribution strip. The power heatsink bars are ultra cheap and sold by the linear feet.

Good luck.

Too many pins would be required to shuffle the data between the hot and cold parts. Essentially the whole hashing chip is hot.

What makes sense is to use a single chip with split clocks and split power supply. One clock and power for the "core" and one clock and power for the "I/O".

The split you suggesting also makes sense for the "full custom" versus "cell library" choices. Use "full custom" for the core hashing round and "cell library" for all the glue logic. But I don't think that the fab the Block Erupter uses would allow them to do this. It seems like they are committed to the cell library only design.

Edit: Here's the link to how Xilinx uses two-process' (65nm and 28nm) split for their $10k per chip Virtex-7 line.

http://www.xilinx.com/support/documentation/white_papers/wp380_Stacked_Silicon_Interconnect_Technology.pdf

Hot hot hot.

This sounds like a job for the Sandia Cooler.

Multilayer silicon is simply not required. The Bitcoin hasher chip is extraordinarily simple as far as digital design goes. The only unusual part is the power dissipation per area-unit. Somebody experienced with power analog design should be able to solve it quickly and without much expense.

It is basically a lottery-ticket buying machine. Even if cetrain fraction of the tickets is mangled the whole machine is still worth it. There will be no yield issues: it will be either zero (completely doesn't work) or nearly 100%.

Great to hear the news of this ASIC project, nice numbers too.

As long as your plan isn't to hold onto everyone's money for months, you'll sell a bunch of these. I'd buy a few units just to support the network and not give a crap about mining returns. I think many others would as well.

Also, if you really hope to have success selling these units, just get them ready before BFL and you're going to sell as many as you can produce.

Yes, especially that the hashing units themselves take over almost all the chip area.


Yes. We made this decision from the start. The typical voltage for powering the I/O is way too high for the whole chip.


Exactly. In fact the glue logic only occupies a tiny part of each chip, all the rest parts are for hashing. And a full custom design is too impractical for us.


Thanks again for your link. :)

We divide our business into two large stages. The first one is to make prototypes consumed by us. The second one is to design higher quality mining devices for selling. Or in the second stage we could find some partner to do the whole PCB/case/repairing/custom service/logistics for us. But both options need more time. So thanks very much for your expectation, but it will be later to deliver nice products for sale than deploying the first batch of chips for ourselves.

Update

We decided to apply more manual optimizations to further increase the power efficiency. Since our chips will be mass produced, we believe some more time spent on making each chip better is worth it.

You might not want to spend too much time on your own miners if your tape-out is successful. I'd do a reference PCB design, test it, and release it asap together with the chips. You'll make much more money selling the chips and maybe licensing the reference design, than by mining yourself. Time is your enemy here.

13 Watts is not that bad, and if you could improve it, brilliant, but it's still in the region of some of the more powerful Intel Atom chips and they are not hard to cool down. Also with going down to 65nm (and lower) designs eventually I assume you'll be going to very low single digits which is awesome, by the nature of scaling.

Great Job !

Of course, but product quality and customers' words of mouth are the life of a company. But we don't want to sell prototypes. We want to sell mining devices with a higher standard. We ourselves could probably handle second-digit rates of failure, some heat issues, and sketchy appearances. But we wouldn't want our customers to have to deal with them.

Thanks for your appreciation. :)

We are on our way of lowering the power consumption down to less than 10W while keeping the same hashrate per mm^2. And please don't rely on the data too much because the back-end stage's power estimation makes more sense.

This is exactly why I suggest you do a reference PCB design, and roll it out ASAP together with the chips. There's no point for you taking care of all the hassle associated with B-to-C sales like warranty, after sales etc. You customers should be mining rig manufacturers or able hobbyists, not end consumers. Sell the chip like xilinx sells spartans. License the ref design PCB or just release it open source. Scale up quick, time is your enemy.

I tend to agree.

I have to ask.  What will be the potential market share when pitted against BFL *if* BFL uses a 90 or 65nm process?

In my mind this would have to be a market battle fought on unit price.

IMHO: I don't think the market share issue is significant at this point. It's all about who's first to deliver and at what price. BFL has a huge waiting line of pre-orders, but looking at their track-record, most people (if any) on that list are not going to receive their product this year (if ever). Even if they manage to deliver something on 90 or 65nm it won't matter as mhash/$ is the thing that counts the most at this point. Their current prices have ~1000% margins (not counting NRE). If someone beats them to market, they'll need to drop the price, or their pre-orders will be the only thing they'll ever sell besides mugs and t-shirts :). Later on, when difficulty rises tenfold and more, the question of mhash/W will have more weight in purchase decision.

Interesting information. Looking forward to the more optimized numbers. I'm sure you guys have thought of this before but, if you haven't, once you guys have a commodity chip you may want to chat with Enterpoint. They've shown interest in Bitcoin, appear to be working quite hard on their product, and their first hardware design was impressive given how little time it took to release. Sell the chips in bulk reels, provide the pinout and let Enterpoint create the PCB, VRM and controlling FPGA to handle a couple of these chips per board. Could be a great partnership and dramatically accelerate the time to market of such a product.

In the end I'm fairly certain you'll recover your costs faster by selling your chips than by mining them yourselves. Especially if you believe that BFL and Largecoin will deliver sometime in 2013.

As most have stated in this thread, you will have nearly ZERO market if BFL or some other vendor beats you to the punch. If you can produce something at a reasonable cost which is cheaper than current fpga's and has at least 5-10x the efficiency, you will sell many.

As miners we don't care about looks or even some bugs as long as you continue to support your product and get us where we need to be.

You just need to make this happen within 90-120 days.

PCB design request...if possible:
1. PCI-E form factor
2. Single PCI-E bay
3. "Plug & play" - drivers, etc..
4. compaitable with majority of miners such as cgminer, MPBM....

Thanks for your question.

There will indeed be a market battle. The question is how intense it will be and when we will reach a relatively stable equilibrium. In my opinion, there's still a long way to go before the market price falls down to the same magnitude to the margin cost. Before that, all ASIC vendors would be quite profitable.

Thanks. It sounds promising. We have thought of this but Enterpoint hasn't come into our mind before. We will definitely do some research on it. :)

+1

a sound business opportunity were all interested parties win...design houses + miner + bitcoin community

Update

After further optimization and some trade-offs, we came up with this updated estimation results based on our improved design.

Hashrate: 1.00GH/s per chip
Area: 21.7mm^2 per chip
Power Consumption: 8.23W

Again remember that they are estimated from the RTL design and might have some differences to real products.

Good progress, that is a massive drop in Wattage, so it's a fair trade off.

I'm a noob when it comes to FPGAs and ASICs, so I apologize in advance for my noobishness  ;D  but with all this talk of BFL ASICs, I think it's about time I look at selling my GPUs. I admit I have pre-ordered a couple Jalapenos, and have bought one single in the past, however I am among those who don't particularly like their business practices, so I am pleased to see a potential competitor.

I have not been closely following this discussion, but I have a couple questions that I didn't see answered.

1. The estimated specs of each chip sound great, even if they end up being off somewhat, however, how many chips will be in each "Block Erupter" device?

2. "~150k$ for 130nm, ~500k$ for 65nm, furthermore much less if you do a 1/N mask" means almost nothing to me  :-[ roughly how much do you estimate each "Block Erupter" will cost to us customers?

3. From the threads discussion, is sounds like this product may be ready sometime by the end of this year? I didn't really see any firm ETA, so I was wondering if there is one available at this point? Assuming BFL actually does start shipping at the end of October/November, is there any possibility this product will be shipping by then?

ASIC is a custom chip, they are a built to order to a very specific spec (for bitcoin mining) and in large amounts to be cost effective, usually over 10,000, however really large orders of 200k make it far more cost effective, but larger upfront costs. It's static, unlike a FPGA, so they can't upgrade it once made, it's why it costs so much generally.
So ASIC can be quiet cheap when you compare them per individual chip price, but it's a big start up cost for the designer. FPGA's are more expensive individually, but you can do more with them, and on a small scale the cost is easier to pass on without hurting their accounts.


Price could be cheaper than what BFL is offering their ASIC devices at since their first designs are on a older, but more cost efficient for them process, while BFL opted for one over 3x more expensive by the speculation circulating their numbers they saying it will do.
It however is far more efficient hash/s per watt. I'd estimate the Block Erupter chips (just the chip) will only be $5-15 a piece, but that isn't all that goes into them and also they have their own profit margins to worry about, so it won't be that cheap. But below $100 would be reasonable, since we know it's less expensive to make them.



FPGA's and ASIC will play a bigger part in bitcoin by next year, personally I do believe the use of GPU's is going to start fading, just like it did for CPU's. It's a matter of time, but it will eventually happen, some are making the step now and enjoying lower energy bills and often faster hash rates.

Thanks, that gives me a better idea of what to expect for the pricing, however I am still wondering how many chips per Block Erupter? I am assuming either one or two, but that would be a rather big difference obviously. Is there a product website up yet? Does a CAD drawing, or actual prototype exist?

I am looking to reduce the power consumption of my mining equipment, but as far as the difference between the efficiency of Block Erupter vs BFL ASIC goes, that matters very little to me, as either way, this is a huge improvement over my GPUs. Assuming they don't get hit with so many orders for Block Erupters that it takes 7-8 weeks or more to ship, I would be very interested in purchasing these if their GHs:$ ratio is somewhat close to that of BFL ASIC. As it stands now, at the very least it looks like that will be roughly 10MHs:1$, not quite the same as BFL's claimed 23MHs:1$, but if a second chip is included with each Block Erupter, assuming a cost of $100 per unit, that brings it much closer to BFL.

Thanks. Yes, basically the more ASICs are produced, the lower the cost per chip becomes.


In fact, the margin cost per chip is less than $0.8 a piece, that is hopefully $0.8 per GH/s. Of course, if we consider the cost of heat sinks, fans, PCBs, power supplies, and the disperse of the initial NRE cost into each GH/s, it will be significantly higher, but still within a single digit dollars per GH/s.


If only considering the whole production cost, it is easy to achieve more than 100MH/s : 1$. The actual market price is another story of course.

:O

That is really low price, amazing. Guess it helps to have contacts in the right place that will do it at cost price for you. Guess I'm a little to use to prices to manufacture them over here in the UK or USA. It would be more expensive.

Thanks for the reply, I'm certainly not expecting 100MH/s : 1$ for the market price, as BFL's alleged SC Single is only 30MH/s : 1$. While it's great news to hear that can be done, I'd say anything around 20+ MH/s : 1$ market price would be an excellent BFL ASIC competitor.

Any chance there is a CAD drawing of the Block Erupter yet?  ;D That would certainly be more than BFL has managed to come up with yet.

As I said, <1$ per 100MH/s is the estimation of cost. The market price for selling will probably be higher.

Currently what we have are netlist files and back-end results in various stages. They haven't been visualized yet. But it's possible that we come up with tangible pictures to share before the production.

So when it comes to mining with an ASIC all you would need to set one up is a cheap PC with a USB port like a netbook and some kind of mining software?

There is now. But it's not named as CAD drawing, but IC layout. :)

The first picture is the IC layout of the whole chip after P&R. The big cyan bar in the bottom center is the pins of the chip. Purple bars above and below the chip, as well as the light blue bars in the left and the right of the chip, are all power pads. The small rectangle in the bottom left is the blackbox of PLL IP module. The rest parts are real hashing units doing the actual job of erupting blocks.

http://img1.douban.com/view/photo/photo/public/p1664317503.jpg

The second picture is a magnified local part of the hashing unit. It's harder to tell which part is which in this picture, but it feels very nice for ourselves to see how our logic design turns out physical.

http://img3.douban.com/view/photo/photo/public/p1664317518.jpg

Yes. The same as current FPGA mining boards. :)

Pictures... I came.

Suddenly there's no more talk: OMG ASIC is gonna kill Bitcoin :)

Awesome thanks.

Nice! And thank you! I will certainly be ordering some of these once they become available!

Looking forward to some competition.
Have you considered accepting payment in bitcoin? Or have you not gotten to the business model yet?

They are raising money to start production through GLBSE and private share placements

https://bitcointalk.org/index.php?topic=99497.0 (https://bitcointalk.org/index.php?topic=99497.0)

Are funds still needed to get this chip into production? I've never purchased "shares" of a company before, not into stocks either, so this concept is new to me.

Personally, I'd kinda rather just give you money in the form of a pre-order for the products, as BFL is doing with their ASICs. Your company seems much more transparent than BFL, and seeing as how you have some proof of existence of your work, I certainly wouldn't mind tossing some pre-order $$ your way, as opposed to BFL.

This is a tempting investment.


Though, it's unsettling to know that after share principle repayment 50% of return goes to a small group of individuals that is Bitfountain.

Conservatively, IMO, Bitfountain's take might be $40,000+ for the first month after funding repayment.  Definitely a sweet deal for Bitfountain.


Bitfountain will always own a minimum of 50% of their self-run hashing capacity.  Makes me nervous the same way Vladimir's plans did.

Wait, sorry if this is a dumb question, but do you mean that Bitfountain is going to be a mining company only, that is to say, that they will not be offering the "Block Erutper" ASIC for sale?

They are planning to mine themselves with 20 TH, then when the investment is paid off sell the ASIC while expanding their own mining operation to 50 TH

Anyone please correct me if I'm wrong

Update

Since the fundraising thread was already made, I would prefer the discussion of more technical aspects in this thread. After all it's a sub-forum in the hardware board. But I will answer these questions:

We will offer our boards for sale, but that will be a stage after our self-mining. Because within that time we could polish our board design and contact potential partners of doing marketing, logistics and customer service for us.

1. We ourselves don't consider the portion of our own too high. Because the investors of ASICMINER will have the privilege of breaking even first and no future dilution. Also the market will tell us whether 0.1BTC per 1/400,000 of the company is overpriced or not.
2. It is hard to say if such a prediction is conservative or aggressive. It might be either much higher or lower than that depending on how the ASIC mining industry performs. And no one knows how many competitors are secretly lurking there besides those who have revealed themselves.
3. We may own less in the future, because when we further sell the shares of the company, we can only sell ours because, as we promised, ASICMINER shares are prone to no dilution.

What this thread is entirely missing is where the production would be done. (masks, wafers, packaging and bonding). And some really good explanation of why it would be so cheap.
No "LOL we are in China" is not sufficient.

Which software is used to design the chips? Where do the models for the gates come from?

FYI: I am almost certain this is a scam.

It usually is. :)

However, are they actually accepting payments in any form, yet?

Or do you think this is all still in a 'foundation laying' stage and the 'amazing opportunity to invest' is still to come?

"Since the fundraising thread was already made"

Hmmm. Ok, I need to go look for that.
Link for convenience, please?

These factors all contribute to the inexpensive cost:
  1. 130nm node size. As the mainstream switches to 28nm, the 130nm existed for so long that even many smaller foundries could do it very well. The intense competition of manufacturing in China brings the price of everything down, including ICs. Though we chose the larger and more reliable foundry, their evaluation of the price of 130nm full-mask and MLM is still near the price in this main thread.
  2. MLM(Multi-Level-Mask). Compared to full-mask, this technology reduces the cost of mask-set to half with the exchange of increasing the margin cost by about 40%. This is a good deal for us because the margin cost of chips themselves is one of the lowest cost in our budget.
  3. Low EDA license fees and low labor cost in China.
  4. We ourselves did most of the RTL design, optimization and simulation.

The RTL is written in Verilog.
Frontend: We use VCS for simulation, Verdi for debugging, DC for synthesize.
Backend: We use ICC for P&R, Calibre for DRC/LVS check, virturso for layout merge, StarRCXT for RC extraction and PrimeTime for STA.

Formality is used to verify the netlist. We also do some simulation directly on the netlist but it is very slow compared to that on the RTL phase, so many possible cases of the state machine couldn't be covered. Formality is needed to increase the confidence of the synthesize results.

By models of the gates, I guess you mean technology libraries. They are provided by our foundry indirectly from the foundry agent.

The PLL IP module is also provided by them.

Please PM me with your e-mail address and ask for more documents and information if you feel necessary. Thanks.

But we are not. :)

The fundraising thread is here:
https://bitcointalk.org/index.php?topic=99497.0

There are more information, as well as question answered.

I would prefer that this Block Erupter thread will be mainly used to report the progress of the chips to the community, as well as discussion of technical problems in the future.

The link is about 5-6 posts above yours, how convenient is that? You take your moniker pretty seriously, eh? ;D

I reckon so. :) But I do apologize.

People who don't read threads before posting do tend to drive me nuts.  :-\

Lol, I wasn't being quite as blunt as it maybe came across, was just giving you what you wanted in my own cantakerous way  ;) We all skim threads and then ask questions that have already been answered (expect the perfect people of course, I feel sorry for those lot! Making mistakes is fun!)

I love this theory. thanks for the asymmetric information, I and other investors are able to invest into this company at such a low valuation, because people like ElectricMucus just don't believe it.

I must say, I much prefer the funding route that Block Eruptor are taking (as opposed to BFL's model). At least there is a better opportunity for ROI both before you receive any hardware and after. And you're not even commited to buying the hardware, you can simply sell your shares if you get cold feet.

Also, 0.1 BTC minimum investment is substantially lower (pffff, and the rest) than $149 for a Jalapeno. Still, I believe that BFL will deliver hardware (eventually). And I can't quite say the same thing for the Block Eruptor devices though... friedcat openly admits that there is some possibility that it will not happen (on the basis that the IPO may be refunded if the minimum is not reached)

But I guess that brings me to another feather in Bitfountain's cap: I wasn't expecting such candid breakdown of the financial details and the manufacturing costs (the figure for the margins on the chips are the sort of thing that you'd expect a commercial operator to keep very close to their chest, especially when directly liaising with future customers).


It's rather difficult to choose between these two!

There is more details being provided here than anything BFL is doing (and historically provides) I know you don't like them either, so for that I believe them more than them. It might not say much, but it's understandable when doing new things in your field you can't go telling everyone everything, without needing to have those answered in confidence.
Maybe not all your questions are answered, but their is a fair amount in the first post (updated) as well as scattered through out the thread, as well as friedcat answering the more techy questions you wanted with your accusation of being a scam.

They are formed in the city of Shenzhen (China), which has a well known technology manufacturing background, many of the "big boys" in tech in china are based in that city. It's slightly more specific than somewhere in china, don't forget a good portion of electronics today are made there, and with it being done on 130nm (old now) it's ideal for their first design chip. Every question the community has asked, he has managed to give a good open answer, his reputation is far better than BFL right now.

I think that's a little unfair on BFL. They have shipped hardware, not particualry successfully, but they're in a bit of an awkward position being first to market (albeit pre-orders). How would you do it?

It's very difficult to do a direct comparison between the two, as their operating models are so very different. Like I said, I prefer the Bitfountain model overall, but that will be completely irrelevant if Bitfountain don't succeed. Under those circumstances, Block Eruptor cheerleaders will be purchasing their units from a parallel universe :D

It's not unfair, how many exact details do you know about the new ASIC product from BFL? Outside of the PR stunt provided info, that already has a lot of speculation surrounding how they will manage those numbers. How far off was the first BFL stated numbers for their singles; massively off because they were guessing. Lab work and predictions based on real numbers didn't factor into it.

Now compare that to what Friedcat has provided that about his. Big difference, he has been more open and provided more answers. They are providing numbers and info from the lab as it comes. It's the same reason why I supported Yohan (enterpoint), they are honest and open and discuss their product. Customer support comes first with these people it makes a difference.

BFL could have been more open from the start like other FPGA developers, they choose not to, it still hasn't changed, Inaba might change this, but it's early days. I however don't think one person can pull it off, if it stems further up the chain.

... sorry to derail your thread Friedcat.

sigh

It helps if you read and comprehend what I actually said. Oh well.

Just because I am critical of your trying to badly defend them based on the difficulty of being the first to market you think I didn't read it? Yes there is many people who could of done it better and given the chance I'm sure they will prove it. I've been a consultant and developer quiet a while, so yeah customer support wise I would of done a lot better job than they did. But it's not my area of speciality, so I support those who's speciality it is and do a good job that aspect.

Of course did read, but it's not an good excuse to use (first market mistakes). It would maybe held up better if they hadn't continued to act the same way with later products. By the fact you keep quoting just a tiny portion of what I say, I could be childish and accuse you of the same (not reading/comprehending). But will it get me anywhere not really.

I am happy BFL finally has a competitor that stands a chance of beating it to market this time.

Oh dear! I do not know how to reply, based on my assessment of the way you appear to think. I promise not to stand up for what I believe to be the case in the future, you've totally convinced me of that.

NOTE: I'm strongly in favour of competition between ASIC hardware developers, as the market competition will go a long way to ensure that unit price and overall hardware qualities will be favour the customers as much as the vendor. Anyone in the market for a SHA-2 ASIC would be crazy to believe otherwise

There is only one way to find out. Get them to release more information. If it is a scam as some people believe there should be no viable designs whatsoever, and if they're incompetent that should be possible to infer too. If we could find an able and willing third party that can be trusted with confidential information we might be able to convince them to release the designs, under an NDA.

Feel free to suggest people. I'm willing to pay for it myself.

The scam callers are also being a little unfair IMO.

friedcat has provided very extensive information, not just on the technical/manufacturing aspects of the product, but on the financial arrangements too. Although my knowledge of microchip production is limited, I know just enough to find his explanations of the issues they face (and how they're proposing to tackle them) pretty convincing. Scammers or not, he and his team clearly do know a thing or two about chip design and fabrication. Ditto the financial arrangements: I'm far from an expert, but what limited knowledge I do have leads me to believe their plan for funding the initial outlay is pretty convincing (although they're presumably not paying the foundry in BTC!)

For all we know, both ASIC companies are scams right now. But based on the evidence we do have, both organisations deserve the benefit of the doubt 

I only have one response to this.

Can you do the Carlton dance?

Haha, this applies to BFL, too.

Before we get a real chip in hand and test it, no ASIC R&D team will be able to assure you the outcome with 100% certainty. The R&D risk of both company are equally huge.

I think both the companies are trying their best to deliver the ASIC mining rigs. It's fantastically profitable after all.  Both companies have the real world/local contacts and identity. It's not likely for both of them to scamming people's money from the crowd for 100k USD.

Given your identity is known, scam money from crowd and from a single individual is 100% different. Don't scam the crowd, scam the isolated individual, that's what happens all the time in the private industry.

This amount of money cannot even buy you a department in Beijing, Shanghai or Shenzhen. The risk for them is too much to do so, considering what they have already achieved in their social ladder climbing effort in real world.

The difference between the two is, BFL funding their venture by debt from their customer, it is not appropriate to do so IMHO without a real chip in hand. What will BFL do if the chip turns out a failure or the hash rate cannot reach what they have claimed? The same situation happened in the FPGA rigs.  I think they will delay the delivering date and accepting more pre-orders to finance their second mask. Friedcat is open and honest to the community, and finance the project with equity. There is risk of failure, but the potential return to be distribute to the investor will compensate the risk much better than BFL.

Well, I'll have you know that me and my calling card are still available to perform at Meet 'n' Greets in well heeled nightclubs and supermarket openings thoughout our glorious nation  ;)

I almost 100% agree, with one proviso: not likely, but far from impossible


Here's where we may depart absolute consensus again: I think that BFL would have a serious problem cutting out now that they and their staff are so well established within the community. It would cause irreparable reputational damage to the company and the individuals involved (look at the whole Zhou Tong/Bitcoin Consultancy issue. Intersango's drop in trading volumes seems to be connected to that, and there's no irrefutable proof of who was responsible as yet.).

The Bitfountain team don't have the same level of establishment within the Bitcoin commmunity. This is not to say that they have none at all, but you could interpret their contribution to this very cynically if you chose: currently, all they have right now is a single individual with ID verification on GLBSE, an IPO that is selling well, an iteration or two of some design/performance specifications, some product diagrams, some insight into their manufacturing issues and not insubstantial amounts of convincing talk in general. Most of that is based on this forum, and it would be a spectacular coup as a confidence trick if they were perpetrating a scam. But I disagree that you think that several months of convincing statements and interactions on these forums isn't worth a six-figure $ sum; it is (and I know that's an unflattering portrayal, I prefaced this whole thing with a cynicism disclaimer! I am, in reality, genuinely considering buying ASICMINER shares)

BFL have something tangible: products available now (admitedly not the best product out there, but a viable product nonetheless). That adds a different kind of credibility to their operation.


Again, I broadly agree with this, and also would prefer it to be the truth. The trouble with BFL is that, of the few details of their ASIC product that we do have, they have not been very encouraging so far. For instance, the hashrate performance figures sound slightly too good in comparison to friedcat's figures (although BFL have quoted per device and not per chip). I can't see how a 65nm process node or a different implementation of the algorithm can really make that much difference to the hashing output. Surely each chip runs a single thread pumping out hashing solutions at whatever clock speed they can achieve with the underlying silicon? 130nm isn't so far away from 65nm, and I expect that there has been further innovation in the 130nm sphere since the desktop computing market has stopped using the process. Surely the SHA-2 algorithm can only be implemented in silicon a limited number of ways, algorithmic content is after all very specific. Perhaps some of those with some expertise could shed some light on this.

And the funding through debt to the customer model does put me off. When's a good time to buy a BFL ASIC? Now, to get a good place in the queue? (a queue which we all know is not going to be satisfied in the same order that the people formed the line) Maybe right before you expect product delivery? Immeditely after product has been demonstrably delivered? Well after product dleivery when the fuss has died down?

All options have huge downsides when you choose the date on which you buy your BFL ASIC. Not so with the way Bitfountain have arranged it.

Friedcat.

Could you offer information on the level of involvement of the foundry in validating the design?  My reason for asking is to understand if the foundry sets expectations for it's customers for failure probability given a specific design.


Thanks.

I have played with mentioned softwares, shown pictures looks coherent. In my opinion success probability would be high for such approach. Tool names, etc match... I will decode what that means - VCS - is simple stuff - it's rather top-level verilog simulator. Verdi - I don't get why you need a debugger.

DC is Synopsys Design Compiler - which is usually shipped as part of ICC (top-level) - Synopsys IC Compiler.
Synopsys IC Compiler basically enables you to feed in gates and get what is on picture, and that is rather quick operation, once your RTL is good. Good sides - it would do layout for you, bad part - manual layout would dramatically for sha256 outperform automated layout, but require dramatically more time + more understanding of low-level stuff, like maintaining heights inside of chip, etc.

Calibre - is Mentor Graphics Calibre - de-facto standard for Design Rules Check (DRC) and Layout Versus Schematics (LVS) checks - DRC is basically checking of multiple design rules mentioned by fab, and LVS is verifying layout vs its schematic equivalence. Usually if you wrote (or get from fab) correct technology file for Calibre that means that your design IS MANUFACTURABLE.

Virtuoso - is a full-featured suite from Cadence - for IC design, compilation, etc... So all could be done in Virtuoso, but package at my taste looks like pain in ass...

Synopsys StarRXCT for RC extraction - RC extraction - is one of important things for design verification, as it provides exact delays caused by capacitors and resistances existing in circuit. Basically it eats layout images, and generates files for further simulations (say for example SPICE circuit can be extracted with parasitic values).

Synopsys Primetime is powerful tool to get perform timing analysis taking data from StarRXCT.

Also there can be run SPICE simulation after StarRXCT to get power consumption for the design.

I am no way affiliated with friedcat, so I can basically confirm for public plausibility of mentioned data, if they (friedcat) will decide to publish PrimeTime reports for
their design and spice simulation to get power consumption...

ALSO PLEASE NOT - THAT LAST THING IS _MANDATORY_ FOR THEM - PERFORM POWER ANALYSIS...... IT IS LIKELY THAT YOUR DESIGN WOULD NOT WORK ON MENTIONED CLOCKS
IN PRIMETIME JUST BECAUSE NOT ENOUGH POWER BYPASS WAS PLACED, AS IN THIS PART DESIGN BECOMES MUCH MORE DIFFICULT THAN PLACING SAY CPU, WHERE TOGGLE RATES DEFINITELY MUCH LOWER. IF YOU IGNORE THIS - IT MAY HAPPEN THAT YOU GET 1/2 or 1/3 OF CLOCK IN REAL DESIGN. Power Integrity could be done with Spice or maybe better specialized tools (easier)... Maybe quick simulation of single round would help you in Synopsys HSPICE or full-design simulation in Mentor MachTa (but this I don't know for sure, how well MachTa suites for power consumption analysis - I think better is work on smaller but regular portion of design using HSPICE, as full-chip sim will go for ages I believe).

MLM asic chip basically tells me that TSMC is foundry, as they widely advertised MLM technology, where you can reduce masks costs 2 times or 4 times or possible even more (it was not advertised though), when you can put several layers of chips on same reticle.

Have you heard of anyone using BSIM4 commercially for the last, 100% analog stages of the verification?

I'm thinking minimum of probably 32 rounds: because of the multiplexer first 16 rounds are different than the remaining 48. From the non-cryptographic point of view one would want to simulate full shift register runs in both two positions of the multiplexer.

Maybe on the merchant, commercial basis TSMC is the only one. But for the more R&D-oriented clients Europractice offers MLM flows through the other fabs.

Anyway, this post is just an excuse to post the link for a really cool chip floorplan porn:

http://www.europractice-ic.com/docs/Annual_report_2011.pdf

This is one challenges for me - there's multiple ways to do it, but basically in flows that I saw before people
use simpler approaches. But - it would work ok for not too-power-hungry designs, while for such massive
crypto they may not work, as number of elements that are constantly switching is VERY HIGH.


Not exactly needed, as you can put on borders of single round construction "mock" flip-flops that will just toggle at 50% of clock speed and feed it with data.
So you can perfectly simulate power consumption.


Do you mean MLM or MPW ? As MPW is multiple projects placed on single reticle, while MLM is same project but multiple layers per reticle, and MPW is usually
compatible with all fabs, but MLM requires fab to place same reticle rotated.

This is interesting. What I've heard is that BSIM4 is the most accurate but also the slowest and least user-friendly. Pure-digital designers are happy using simpler models and more streamlined tools. It is more of a tool for the analog and mixed-signal designers. On the other hand BSIM4 is free, only the model parameters are secret and cost money.

Oh I see, a miscommunication. You meant single physical round design sorrounded by a T-type flip flops, but run for all the cycles of the whole computation.

I also meant single physical round design but also shorten the required count of cycles: 16 from the first phase and 16 from the second phase. To account for non-zero boundary conditions use standard modeling practice of topologically stitching top edge to the bottom edge and left edge to the right edge. This is cryptologically incorrect. But it is verifiable, and completely accurate as far as thermal, electric circuit and transmission-line behavior.

Actually both. See page 8:

Well. Maybe I am wrong, but for node sizes till 130 nm BSIM3 seems to be enough, and even for 90nm seems to be adequate. This should be enough to do +- 20% correct simulations.
For Analog / Mixed-Signal - it also depends what you want. As you may do multiple circuit tricks to actually less depend on MOSFET parameters / models and do "software" calibration stuff. Some corporations probably has BETTER models (likely say for Intel), but these won't be available to any of foreign to intel asic developer, etc. BSIM4 are more rich - but for BSIM3 I have data for example for TSMC for MANY real silicon runs extracted + also for many more foundries... This gives me ability to look for actual model parameters variation from foundry to foundry and for each tape-out. So this way for example opens potential to design foundry-independent layout.

This is what I am messing now with - I would like to get simultaneous modeling and layout flow for multiple technology node sizes. Do it once and then scale down as far as needed.


Yep :-) Exactly :-) Do you care at power simulations that cryptography would be correct ? You don't care... You can even look at single round with round expander as huge hierarchial macrocell that do magic :-) But you need to know - how much power that magic needs and what clock it needs, and what are driving strength on boundaries and capacitances on inputs.


Nice ! Really nice ! I think that I'll go with europractice for trial tape-outs, as their access to fabs are good as well as prices are acceptable.

Thanks for your reply. Where I wrote "BSIM4", I should've written genericly "BSIM-family". I played only with BSIM4 and only on an artificial model that was intentionally non-realistic but at the same time consistent with the solid-state physics. A classic educational toy.

Good luck with your designs.

@friedcat

Will you be testing the ASIC processor/board out on the bitcoin Testnet to demonstrate it's hashing power to the public prior to release?

What in my mind has been directly mining on the main blockchain and relay it with the pictures of mining devices to the public. Would you please elaborate the advantages of doing it first on the testnet? Thanks.

Mining in the testnet with such a power would be some sort of posing (or if you want call it 'marketing').  12 Thash of mining power should have a noticable impact on global hashing power, even if a lot of GPU-miners  stops mining.

I say let the numbers speak for themselves (i.e. the amount of BTC mined in the 1st 24hrs  :D)

No need for a testnet demonstration....

My apologies, I didn't make myself clear.

Your IPO terms/information in this thread states that you will mine with the initial batch of hardware produced. It is not inconceivable that some changes to the final device will take place between the first batch of boards and the batch that you actually deliver to retail customers. So, your performance photographs will be of what are effectively prototype devices, not of the retail device. Is this correct, or have I misunderstood your terms?

Hi, Lately I came across this page >> https://en.bitcoin.it/wiki/Hardfork_Wishlist#Major_structural_changes << and there's something I want to ask regarding this:
Will it possibly disrupt Block Erupter's algorithm?

It's mostly a Cryptographic changes, that would be an issue, but as long as it still uses SHA256, it should be possible to still use it, minor software (mining) changes needed could cope maybe?

How is this project progressing now?

It would be nice to know if there is any performance or prower savings between 130nm and  65nm?

Quoting for the record.

Update

Chip Specification
Technology Summary:
  130 nm
  1 Ploy
  6 Metal
  1 Top Metal
  Logic Process
Core Voltage: 1.2 V
I/O Voltage: 3.3 V
Core Frequency: 335 MHz
Core Frequency Range: 255-378 MHz
PLL Multiplier: 28
Power Consumption: 4.2 J/GHash
Number of Pads: 40
  22 Data
  18 Power
Package Type: QFN40
Packaged Chip Size: 6 mm x 6 mm

Chip Interface
Data Pins (22 in total):

clk                    i
soft-reset             i
reset                  i
cs                     i
addr[6]                i
data[8]                i/o
w_valid                i
w_allow                o
r_allow                o
r_req                  i

Address Allocation:

0-31    writing midstate
32-43   writing data
44-47   reading nonce

awesome! finally some real technical info from an ASICs producer.

How reliable is the power consumption figure?

It's the back-end simulation result with 1.2V and 335MHz.
It depends on the actual voltage (1.2 typical, over-voltage and under-voltage is OK), the frequency you set for the chips, and the how well each individual chip could perform (random factors when producing).

Isn't the big pad connected to GND (so the number of power pads should be 19)?

As a past ASICMINER shareholder, for about an hour :), I'm simply curious about the changes within the specifications.

If the wattage has been lowered to from ~8 to 4.2 and the package area reduced from an estimated 21mm sq to 6mm sq. can we assume that additional sacrifices in hashrate were made to accommodate the smaller package and reduce heat issues?

Yes. Thanks for clarification. We use the standard QFN way to package.
So there's a big pad in the middle, making the total number of pads 19.

Yes. We did sacrifice some hashrate per area, that is, hashrate per wafer. But the compromise is worth it, because the loss is not significant, and because we have gained much lower ir drop and much better power efficiency.

Do I understand this correctly if I conclude that one chip will mine @ 335MH/s  ? or 378MH/s if it's a good one ?

or is there more than one stack in each chip ?

Yes.

255-378 MHz is the result of the back-end simulation under 1.2V. If you do an over-voltage, it will probably be significantly higher, but the stability is hard to say. Exactly how high a frequency we could push them to, could only be answered when the chips are out.

Did you plan to sell some ? In such case do you have a price grid yet ?

They are Part of asicminer/bitfountain and will be sold in the near future.

I think there is confusion between MH/s (mega hash per second) with MHz (mega hertz, clock frequency).

No.

Current implementations are made so each clock does one "turn" of the sha256 algorithm, but on multiple stages, usually 128 to make a complete 2-sha256 bitcoin full computation (sometimes called a "stack" )

So 1 chip with one complete stack gives 1 complete computation each clock in such implementations, and therefore Mhz = MH/s

That was my question : is there only one stack in this chip ?

If you had 2 stacks in the chip, you would have had MH/s = 2* MHz

This is only true for most of the used designs. At least bitfury has the sea of hashers aproach where each hashing core  needs 68? cycles to compute a hash but it turned out that it allows  a more effective device utilisation.

As far i understand the discussion between bitfury and friedcat the sea of hashers aproach was at least taken into account.

Maybe friedcat could produce a prelininary datasheet that would be sufficient to design a pcb. I am curious if the pll multipliert is fixed which would finetuning for each chip would be a little more complicated than just setting a register.

Very good. Very good. More evidence that I will win my bet (http://betsofbitco.in/item?id=665)

wow. You sure are a glass is almost full kinda guy :)
1/4.2 = 238 MHash/J
So what you're saying is that BFL, who have not provided any evidence that they actually participated in chip design and optimization (if they have please correct me and post a link) outperform ASICMINER by almost 50%? You know that friedcat et al. spent a lot of time on optimizing that figure?

i've no idea what the impact of this would really be - but the chips discussed above are tiny. TINY. 6mmx6mm is smaller then most of my fingernails. what impact would a large chip size have on the whole hash/joule thing? the FPGA's in the oroginal BFL single are what, 3 or 4 times that size? larger, fewer chips = better power maybe?

...yea, i can't even convince myself on that one.

Jutarul, arklan: what makes you think BFL will use an old 130nm process like friedcat did?
Power efficiency increases with the square of the transistor junction area.
Do the math at 90nm, or 65nm.
I will win the bet
;)

If you disagree with me, please do bet against me on betsofbtco.in!

If your plan was to make advertisement for your bet, you succeeded. If you have information on what process and supplier BFL is using please post the corresponding reference links. The processing technology has indeed a huge impacting on power efficiency, however, as friedcat has indicated, design optimization is even more important. Also, AFAIK with the decreasing nm figure the MASK becomes more expensive and the design process takes longer to keep the chance for failure to a minimum... (?)

True, but this doesn't affect J/GHash. However, I think at least for first generation of ASICs, production costs will be more important. That's why I like ASICMINER's model.

And its the packaged chip size. The naked die could be many times smaller. I wonder what the rationale is for making such small chips? Small chips means higher yield, but on a mature process like this, yield  wouldnt be a serious issue for anything below 100mm2. Packaging, testing, assembly, cooling,   PCB costs etc would make this a bad trade off I would think.

Friedcat can you say how small the actual die is and why you designed it so small?

The main reason is that it makes the iteration cycle shorter and reduces the potential risk/complexity. This is our first ASIC project and our main target is a successful production. Any technical challenge should be avoided in the first place, rather than confronted with a lot of time.

reasonable. get the process down and understand it inside and out first with something small and simple, THEN do the bigger, more complex stuff. very reasonable approach.

...i want more shares now...

Will there be any way to purchase units using ASICMINER shares?

Just wanted to toss in my thoughts on the project:

First, get over the smaller is better idea, Yes smaller gaps are nicer for lesser power consumption but it isn't essential. Most miners aren't going to care of the unit is a square foot or 3 square inches... as long as it does the work, and we don't have to modify the cooling.

What you should really look at is... using very large silicon with the gate structure being shallow and very very wide. What if you were able to process an entire nonce in a few cycles through a massive asic gate array... that's only as deep as it needs to be to to generate a single hash.

The amount of silicon wouldn't raise the price that much since you'd simply be making the process much more modular that current designs, and duplicating it over a much larger number of chips. You would raise the cost having to custom enclosure and heatsink for the large hardware. . . but you could recover some of that by using a larger process (90nm?).

The issue with this design is you need to have the software already optimized before making the hardware.

The downfall of designs in EVERY other asic manufacturer, seems to be using 'as small as possible chips' then having to run them at high clock rates and having them do repetative incremental work. Creating a need for custom cooling and stupidity like cooling the bottom of the pcboard with a mosfet cooler (yah BFL I said it).  When the design goals should be exactly the opposite (aka load entire noncerange, process entire noncerange) then output flush and start with a new nonce range.

I think you're suggesting that unrolled cores are the answer. They aren't. You run into timing problems, and you also pay for that silicon to be produced no matter how sparse or packed it is. The best option seems to be iterative rolled up cores that take ~110 cycles to do a nonce, but you have ~100 times more cores.

Plus, it increases yields as the controller hardware can just test which cores work and ignore known broken ones (ie, intentionally binning parts ala modern GPU design).

I'm not familiar with the term unrolled cores... I assume it's a bastardization related to how you might unroll loop iteration on an x84 cpu?

Why there be timing problems, we'd have a relatively slow cycle time... and thus plenty of time to check and/or error correct.

Yes, its just like unrolling loop iterations, but in hardware. You have timing problems because you have one clock pulse per hash and everything needs to arrive into their stages at the right time; if you have traces that are too long or too short then stuff doesn't function correctly or you need to waste more silicon trying to properly synchronize data.

It is much easier to just keep data exactly where it needs to be and iteratively process it.

I agree it's easier... but it isn't better. Which was of course, my entire point.

No. As bitfury demonstrated in practice, tiny hashing cores are superior to unrolled designs. He gets 300 Mh/s compared to 220-240 Mh/s for the competition, on an LX150. Some of the gains are attributable to overclocking and overvolting, but most come from its superior design.

No. You said it yourself "on an lx150" - the correct way to do this would be to use dozens or hundreds of chips and have it process in a single stage... impractical on an FPGA, but perfectly doable for an ASIC.

That's because the routing really sucks on Spartan-6 FPGAs. I'm not convinced an ASIC would have the same problem.

firefop, I think you are confusing 2 aspects which are orthogonal to each other: the die size (large or small) is mostly irrelevant to the type of design (tiny hashing cores or large unrolled cores).

For one, even a large unrolled core core would fit in a chip smaller than BFL's SC (56.25mm2 at 65nm). So no matter what design you choose (unrolled or not) you can put as many cores as you want to target whatever die area you want.

You guys claim that routing is not an issue on ASIC, but this is incorrect too. It is less of an issue compared to FPGAs, but it still is, especially for SHA-256 where you have 256 bits of state to manipulate. If you are familiar with the algorithm, you should know that this state (A..H) is rotated in the main loop, so the 256 bits are used all over the place, and create routing challenges. This is less of an issue with a non-unrolled design, as the state can be kept close to the tiny core.

It would, but because heat and (lack of) voltage (to prevent more heat, causing stability issues) would become much more apparent on more complex designs. Spartan 6s just make the problem seem a magnitude or two worse than it is.

I can confirm that Bitfury's bitstream runs at ~305 Mhash/s on normal voltage range as per Xilinx specs.

The argument for the sea-of-hashes design can be derived from the classic analysis made by Mead & Conway and contemporaries.

Consider a circular sea-of-gates big enough to implement many copies of the Bitcoin double-SHA256.

SHA256 is basically a pair of 32-bit wide shift registers with some somewhat convoluted feedback logic. The feedback logic is active (doing the actual computation) whereas D-type flip-flops and connections are passive (just shuffle the signal around). Let X be the average connection length in this design.

Now think about unrolling the above design over a plane. You'll need the values of the feedback terms from the neighbouring cells w-2,w-7,w-15,w-16. Your average connection length rises (2+7+15+16)/4 times or about 10*X . So the passive losses in the interconnect rose about an order of magnitude. You could compensate for this by removing some D-type flip-flop stages and slowing down the clock. By definition you can't really remove the active logic gates that compute the feedback terms. As an extreme you can have a purely combinatorial SHA-256 hasher doing everything in single cycle of a rather slow clock.

I'm not aware of any neat analytical solution for the above optimization problems. But the numerical experiments show that racing the combinatorial signals over vast expanses of silicon is a losing game. Speed of light in MOS transmission line is much less than the speed of light in vacuum. This analysis can be made without actual place-and-route, it is sufficient to have an estimated distribution of the inter-connection lenghts that create planar graph for the logic. I don't recall if sphere-of-gates instead of sea-of-gates is a win, but sphere-of-gates has an obvious termal problem even if we could somehow manufacture it.

In summary: wafer-scale integration was attempted several times in the past without an obvious win. Check out the history before you follow that trail.

So I see what's going on in here :)

My post in the shareholder thread that seems should be in here:
https://bitcointalk.org/index.php?topic=99497.msg1350329#msg1350329

Hey friedcat, if you give me one of these, I'll make sure DiabloMiner supports it.

Fixed that first part for you... but just wasn't up to trying to edit the rest for conceptual logic failures.

Software optimization isn't the same as hardware optimization. ASIC design should not be thought of as "lets make a chip that can do this calculation at 2000mhz over and over and over..." that's counter-intuitive. You've locked yourself into thinking in terms of GPU design which need not apply to other processes. The reason GPUs (and yes, CPUs too) are designed this way is because they are multi-function chip. There's operations they know how to do, and they process things according to instructions. That's fine for generalized applications. In the case of GPU you've got a hard limit / goal of producing a video frame every so many fractions of a second... sha2 just doesn't need that level of coordination. You aren't having to work for a variety of instructions - it's a single process that doesn't change.

Besides which we're not actually talking about that much data. sha2... we only need to work with 512 bits at a time. At the very least we had better be unrolling the chunk processing for so that it isn't looping... that's hardware design 101.

Oh yeah - and make sure the MCU guy stops it from producing a serial device on Windows
(doesn't matter on linux, but that will stop it on linux also of course)

All code with ASIC should be using USB direct not serial-USB
And having the serial-USB can cause problems on windows (and usually means a manual driver fix)

I've been screwing around with this for the last few weeks on an MMQ-FPGA converting it from serial-USB to USB
only to find all the windows problems were driver related - not my code.
Lucky I've had access in IRC to the guy who does libusb, to help me sort it out :)

My reason for doing this was to prepare for the ASIC devices from each of the companies - and I'm glad I did do it in advance - coz the problems have been rather annoying.
Of course there will be other issues when dealing with ASIC, but of course I can't do anything about all of them until I have the devices.

I think (though not 100% sure) the serial-USB device's existence is decided by the firmware so it can be fixed after the fact anyway?

The 72 misconception is really getting boring.

FIPS-180-2 defines SHA-256 in terms of two arrays of 32-bit words:
H[8] and W[64]. 8+64=72. Yet a quick comparison with SHA-1 shows that the same "alternative implementation" can be used for SHA-256.

In case of SHA-1 the "original implementation" is H[5] and W[80]; while "alternative implementation" is H[5] and W[16]. Thus: 85 vs. 21.

In case of SHA-256 we have 72 vs. 24 (H[8] and W[16]).

The further observation is that the "arrays" or "circular queues" in the FIPS-180-2 definition aren't really accessed randomly or in any variable order. Therefore both H and W can be converted to 32-bit wide shift registers, but with unusual feedback functions.

The above is just for pure SHA-256, without any Bitcoin specific optimizations. At least two people claimed to be able to apply some unspecified optimizations to Bitcoin hash expressed as a binary function:

1) killerstorm
https://bitcointalk.org/index.php?topic=55888.0

2) Gareth (BitInstant)
https://bitcointalk.org/index.php?topic=10661.msg557579#msg557579

but nothing came out of it. By now pretty much everyone knows about the fact that one can shave 3 last rounds from the 2nd SHA-256 in Bitcoin: instead of looking for zero 32-bit word at the most significant position in H; take an advantage of the fact that H is a shift register and last 3 rounds simply shift the would-be-most-significant-word. So look for a negation of a specific constand value (0x3c6ef372?).
 
I'm puzzled by this part. I never mentioned CPU nor GPU. I tried to pattern my argument after the sort of arguments that were being made around 1980 during the http://en.wikipedia.org/wiki/Mead_%26_Conway_revolution . Perhaps you were mixing me with someone else?

1) Firstly, the double sha256 is a total of 3 rounds (with 64 steps each) - just the whole first round is constant across a full nonce range.
(commonly known as the midstate) that you only need to do once per nonce range.
2) Secondly, the first 3 steps of the 2nd round are constant across a full nonce range.
3) Thirdly, some of the W values are also constant across a full nonce range (easy to work out which)
4) Then finally, as you said, you don't need to complete the last 3 steps of the 3rd round.

In ASIC terms it would be risky to implement any of 2, 3 or 4
While you may gain a few % overall (6 out of 128 steps plus W optimistations) it also means you can only sha256 an exact BTC block header.
If BTC continues to use sha256 but makes any changes to the block header, then that wouldn't be a problem if none of steps 2, 3 or 4 were implemented in the silicon, since you could change the firmware to deal with a different header.

I'm presuming that you had problems with the usbser.sys from Microsoft. Did you also had problems with the Prolific/FTDI drivers as well?

On the LPC1343 like ModMiner yes. ngzhang used hard serial-USB chips (Prolific or FTDI) in his designs. Same with Enterpoint (FTDI).

Thanks. I'm quoting this because it is a very nice reference for the state-of-the-art GPU/FPGA optimizations. I remembered the 4) on your list the most because it most clearly shows the shift-register structure inherent to the SHA-256.

Edit: Note to self: Kano is swapping the standard terminology: step vs. round. Using standard terminology first SHA-256 hash in Bitcoin consists of 2 steps of 64 rounds each.

At least for the chip discussed in this thread it appears that the block header structure is fixed:

Yep I mixed them around - oh well - fortunately it was obvious :D
Thanks for correcting me.

I've only done the MMQ so far. Though the code is 'done' and in my git I haven't sent the pull to cgminer yet coz I've had to rebase it and there seems to be a bug in the ~2k lines of code I've changed that I still have to track down :)

Most likely I'll try Icarus/Prolific next and find more obstacles :P
(unless I get side tracked on something else ... an ASIC device shows up? :D)

The Windows driver work around, in the MMQ case, was to use http://sourceforge.net/projects/libwdi/files/zadig/ to force it to use WinUSB (on WinXP)
So it's not insurmountable - but best if not every windows end user has to do that.

I've bitched about Serial-USB for a long time but only recently got around to doing this USB direct implementation

Firstly, I've only been messing with USB for a few weeks, so if anything below is way off - let me know.

Guessing at the early figures and considering around 50GH/s from a single device using 1 diff shares, and that USB has a standard transaction time of 0.125ms for 480MB/s USB 2.0, there already isn't a lot of space (and txn time is higher for 12MB/s, 1ms)

50GH/s is 11.6x1diff shares a second on average so just dealing with 6 transactions for that (send work, verify, request, receive, request, finished)
You're using up almost 1% of the USB for a single device (0.87%)
There's of course more overhead (device status e.g. temperature or anything else available to be monitored) but 6 is pretty much the minimum.
Add 10 of these devices ... and I've no idea how well USB works running at ~9% capacity (and how that affects other USB devices)
Also, if the device is idle for even 1ms waiting for work, that's more than 1% of it's work time lost
Thus why I'm certainly using USB direct for all ASIC USB devices - not Serial-USB and adding more overhead on top of it (and timing issues)

Down the track, once the first version ASIC devices have been optimised more for hashing performance (e.g. adding passing share difficulty to the firmware if not already ... or even going as far as implementing something like Stratum in the firmware) this will reduce the bandwidth usage of a single device, but then again it shouldn't be that far down the track when 50GH/s per USB device might increase substantially.

Thank you for the writeup. I'm not really familiar with building clusters using USB, I always worked with real serial HDLC/RS-232/RS-422 controllers or with Ethernet multicast.

The only real USB experience I had was with FTDI USB controllers. Neither ngzhang nor Enterpoint bothered to route all available signals from the serial chip to the FPGAs, so the high-bandwidth low-latency modes of transmission couldn't be used with them.

Hopefully the ASIC controller designers won't make the same mistakes and will allow you to use isochronous or bulk modes when the bus utilization becomes non-neglible.

Anyone know which way friedcat decided to go with this? ie.e sell hardware, shares, selfmine?

See this topic: ASICMINER https://bitcointalk.org/index.php?topic=99497.0 (https://bitcointalk.org/index.php?topic=99497.0)

The first 16 TH (roughly) will be used for mining for the company, then the mining farm will be extended while the ASICs are sold to the general public

I came in late, is the project still going forward despite all the GLBSE hoo ha?

Check the ASICMINER thread. Everything is still going, friedcat is just waiting for Nefario to send the list of shareholders.

Heh. There is exactly one prior FPGA mining setup I know of that speaks native USB - my toy 25 MH/s miner which isn't actually running at the moment. (Implements USB 1.1 on the FPGA itself using a cheap USB transceiver chip. Never caught on with anyone else for various reasons.)

Edit: Also, there's actually a 5th optimization you can do that's very worthwhile in FPGAs - you can push part of the computation of T1 into the previous pipeline stage/clock cycle to the rest of the SHA-256 round, which doesn't affect the amount of logic but does shorten the length of the critical path and increase your maximum clock. I think there are a few tricks with the W computations too...

OT but yeah this is all the crap that Luke-Jr keeps going on about claiming cgminer is a fork of his miner - coz he wrote the first FPGA Serial-USB driver in cgminer ... that has been recoded in almost every possible place that matters since then ...
... and he started the whole problem I'm removing ... :P

Code done already for the ModMinerQuad - as my first step in the lead up to ASIC - so I could do something while waiting - should be in cgminer RSN :)

Interesting however, that from a hardware point of view, USB itself may end up being the bottleneck in processing in the not too distant future.

So ... who's planning a better hardware interface :)

I had always imagined that if ASIC boards were produced at one point, we would connect them to PCI express x1 slots.

No point in using a more expensive controller for the ASIC plus have more limited room and power availability.

Easier to just build large scale 2 or 4U boxes dedicated to the task.

If we're just going to transfer data & not draw any power,how about SATA.It's very fast & most mobo's have several extra & a card can installed to add more  8)

I know as of now its only for hardrives,but can a perephrial device work on SATA  ???

Are you retarded, or just trolling?

Are you doing an Inaba imitation?

He put out an idea. It might not be a good one.

Tell him the downsides of the idea rather than just be insulting.

I guess I'm retarded...........just a thought  ::)

Why wouldn't it work  ???

You are not retarded.  D3 is being a little harsh. 

SATA phy would work, but a serial protocol is needed that does not incur contention present with a large number of bus nodes.  SATA data link is not appropriate since it's a ptp link.

A cascade/daisy chain linkage of sata phy ala the mini rig sc is a good example.  Still need a protocol.

When it comes to connections, something which supports broadcasts may be good. You can feed data in one burst and collect only those data blocks (results) which are interesting - this can be done on a p2p basis. Broadcasts can also be emulated in node based system where the p2p connections are distributed as a tree. However, that requires the nodes to have an understanding of the global layout.

I'd like to review an expert opinion on ethernet vs. USB interface. Any good links?

With Ethernet, the miners would just be emulating the miner interface itself (ie, directly connect to bitcoind).

Does it support UDP? Otherwise the handshake imposed by the TCP connection could be a problem in a scalable design.

Why does a bitcoin miner need a high bandwidth interface again?

People mine on pools all the time on sub-megabit internet connections.  Why are USB's multiple megabits not fast enough?

Am I missing something here?

ASICs crunch the numbers much faster. That means that the time to sweep a full nonce range is significantly shorter. Dependent on how much chips feed from a single master, the time to establish a connection can become rate limiting. Thus a communication protocol which avoids unnecessary handshakes and delivers new work to the chips continuously can be beneficial.

In any event, you want your communication protocol to avoid down time for the chips. That means once the chip is thru with some data, the next data should already be loaded and ready. So I guess you want to plug a few chips behind a controller, which handles all the communication and pushes work into a on PBC board memory.

How did the pools do it? Did they add additional servers on demand? How many GH can work off one server?

Tank ew berry mcchh 4 esplanin dis ta ma  :D

http://i1110.photobucket.com/albums/h451/shymartinez1/SOUTH%20PARK/410463-south_park_timmy_290x400_1__large.jpg

Bitcoin JSONRPC doesn't do TCP, and UDP isn't recommended for reliability reasons. Existing miners don't have issues with TCP because we keep the connection open over long periods. Plus, even if you don't, each mining box itself (no matter how many chips are on it) would have one controller. Modern machines can handle a million TCP connections concurrently without breaking (usually its the software handling the connections that fails to scale long before any OS's given kernel breaks).

I don't recommend machines implement their own miner though: leave it to the experts like me and ck.

Okay, another dumb question then... Can't you tune the expected response time by picking a lower target?

No, because ASICs, just like any other miner, will be looking for diff 1 candidates (ie, H == 0).

https://bitcointalk.org/index.php?topic=130795.0

DiabloD3, as much as I dislike BFL, luke-jr actually postponed their shipping date from dec 2012 to jan 2013. He quoted ngazhang with Avalons shipping date. And I agree with him that as long as ASICMiner is not offering any consumer-products, it doesn't go on to that page.

I suggest you wear your mod-hat with ice inside it, as you must remain objective when moderating. Calling luke-jr a BFL shill in a pinned topic is a bit harsh, and just shows poor judgement as everyone know how much you loathe BFL.

so now everybody hates ASICMINER?  where did this come from...  just because some think they are building centralized farm? IIRC they want to sell the hardware later..

My guess is it is because people are starting to doubt BFL ever delivering.

The 50TH farm ASICMINER wants to set up will be deployed over a period of months. Back in the day when this project was started up BFL had already sold 100's of TH in pre-orders with a promise to deliver in October 2012 as they had "learned from their mistakes". ASICMINER and its 50TH farm would have never been a problem if BFL had delivered.

Now people are seeing it as a threat as 50TH would be enough to take over the block chain should BFL fail to produce a single working chip.

But it would not  be in the interest of the shareholders if ASICMINER became a threat to Bitcoin as the value of BTC would plummet.

Should BFL go bust then I think it is in everyone's interest if ASICMINER changed it's business plan to make sure everyone understand and sees it is not a threat to anything or anyone.

As it stands at the moment, ASICMINER will be the first ASIC around and small enough to NOT be a threat to Bitcoin. Doe sit suck for people that invested heavily with BFL, of course it does.... but does that mean that ASICMINER is a threat? NO !

Look at the entire changelog. He removed ASICMINER completely from the wiki.

gmaxwell has on a number of occasions edited my posts for no reason, and on a few occasions deleted my posts coz Luke-Jr asked him to - with no basis to actually delete them other than lies from Luke-Jr
I'm not sure why you would wonder about what gmaxwell does.
He's Luke-Jr's lapdog of course.

lol http://dramatalk.org/

As I already said,  I agree with luke-jr that as long as ASICMiner is not offering any consumer-products, it doesn't belong on that page.

Technically, if he removes ASICMINER from vendors he has to add them to contractors... Due to the relationship between planned shareholder dividends and mining profits...

okay, so, can you tell me, what company is actually offering ASICS right now? (pre-orders with multiple delays dont count)

so just remove the complete ASIC section of the hardware comparison wiki... it doesnt really exist

It makes sense for the wiki to document upcoming consumer products.

I don't really think that's the case.
People are trying to make profits, and thats why they purchase a ASIC. Whoever seems to be first, or have an idea that might take their profit vanish (or lot less profitable) will be their enemy's.

Earlier it was BFL when they announced (** oh no, can't be true, scam scam), then it became bASIC (after BFL postponed), then people turned over to Avalon, and now it's ASICMINER.

I think that's how people reason, unfortunately human kind are sons of bitches every one in a while ::).

Update

After a long and anxious waiting, we have finally got our packaged chip samples at hand. Everyone would be busy in the following 2-3 weeks.

The following pics are taken from my cellphone.

30GHash/s of computing power on one table:
http://img3.douban.com/view/photo/photo/public/p1823831858.jpg

Top and bottom side of the chips:
http://img3.douban.com/view/photo/photo/public/p1823831931.jpg

A closer look at our baby:
http://img3.douban.com/view/photo/photo/public/p1823832020.jpg

I came.

 :D

30ghs with 120 chips ? What's the hash-rate of single chips ?

95 chips.  That'd be 315.789473684211MH/s per.

W000000000T!

A 5830 in a 6mmx6mm package. Pretty sweet.

Congrats ASICMINER on being first to the party. I hope your chips work.

And so the first true bitcoin ASIC photos arrive. If the chips work as expected the mining community will soon be changing.

Too bad it seems I have gambled with the wrong horse so-to-speak  :P

Most excellent!  Now let's see if this engineering team did a better initial job than BFL and bASIC.

Actually, they aren't yet "first to the party"
I'm pretty sure some of the other ASIC vendors have been in this situation already.

However, none of the others have survived the next step yet ...
If ASICMINER survives the next step (a finished working device), then yes they will be "first to the party"

They are, however, first to actually show pictures of chips - nice :)

Please invest your profits into a manicure, thank you.

Does this mean you need to put 95 of those chips in a single device to get the hash-rate that a bfl little single (30Gh/s) is supposed to give?

I don't see why this is a problem. As long as the cost and power consumption of the device is reasonable, who cares how many chips it has?

More chips means more PCB area, and more traces to route.  How many pins do you suppose are used on those QFN-40 packages, and how many of them need a dedicated connection to the MCU per chip rather than being able to be chained together bus style?

Also consider that a 30GH/s device based on 130nm technology may consume as much as 200 watts.  Depending on what voltage the chips run at, that can add up to quite a few amps that the power-bearing PCB traces will need to be capable of carrying every step of the way.

Cooling complexity will also increase with the chip count, more decoupling caps will be needed, etc.


So they're going to need 38,000 chips to reach their "first batch" hashrate of 12TH/s.  Yowza.

So when will the first full batch be ordered/shipped?

It would be possible to know which is the manufacturing cost of a single integrated?

+1

How does it cost to produce an ASIC chip once the design is all done?

In the case of Avalon: $4000-5000 per wafer, 4055 chips per wafer, $1/chip: https://bitcointalk.org/index.php?topic=120184.msg1402474#msg1402474

Must be without packaging?

Correct.

Hrm, if they're aiming for 66gh per unit, and each chip does 0.75gh, its approximately 88 chips per unit. Packaging and testing cost is, what, another 50 cents per? And completing the product (PCB manuf, mounting components on PCB, etc) is another, say, ~$120 per unit? Thats only a 5x markup from the sales price, how are they staying in business? =/

As you may recall, the $1,299 price was only meant to be for the first batch, and was to be $1,999 thereafter.  Only after the competition threw down did Avalon make the $1,299 price permanent.

Are you still going to be using your customers' money to buy more chips for yourself and directly compete with them (and thus gain significant unfair advantage,) or did you axe that idea already? If you did, then for those of us that purchased shares (and yes I did buy some few of your shares) on the original business plan that actual mining equipment would eventually go out to customers, at which point you would no longer grow your mining business past its original maximum, how have you explained this change?

LOLing at "unfair advantage". It's a free market.

I am in shock! Are people seriously running numbers on Avalon ASIC using BFL as a base of measurement? Aside from the bold statement above, everything else is false. At this point I consider these statements slander: giving the public an impression Avalon is very cheap to produce and the fact of the matter is it really isn't. To put in prospective, a decent PSU is ~$90.

perspective

Saying I used BFL as a base of measurement is slander. I forgot about the case and the PSU, so don't get your jimmies rustled.

Only if thermal pads (http://en.wikipedia.org/wiki/Thermally_conductive_pad) are used.  Otherwise, the height and angle of the chip package surfaces is not likely to be uniform enough to ensure good thermal coupling with all of them.

Twat..... learn to handle semiconductor packages correctly.

Hope those things aren't ESD sensitive.

0.01BTC says they are

Your definition of "free" is strange.

As a shareholder, and ostensibly one of the people who funded their operation, they are potentially destroying the value of my shares, depending on 1) how much they're actually going to pay real shareholders, 2) whether any devices will be for sale to the general public, 3) whether shareholders can buy devices above their shareholdings, 4) whether they're going to use customer money to expand their mining operation in contravention of their original business plan, 5) whether shareholders are going to see any money from the sale of mining devices.

I haven't seen any hard numbers or descriptions of anything yet.

And yet you bought shares without knowing the answers to those questions...

This discussion is off topic. Kindly take it to the ASICMINER thread.

Thermal pads aren't magically bad here, though. They have high end ones that conduct as much heat as shitty paste and only slightly less than high end paste (that no OEM ever uses, they always use the shitty paste on GPUs, or shitty pads on CPU HSFs).

These chips are probably sane at higher core voltages than what friedcat has announced (1.2v), but the problem is heat output. High end thermal pads would still work well here because the chips simply don't get hot enough to warrant paste (and like I said, OEMs don't even use high end paste, even ASUS's ultra expensive premium GPUs with the triple wide coolers use generic paste, which is kind of a shame).

AlCu alloy heatsinks (light like Al, heat conductive like Cu, half as expensive as pure Cu) they use in low profile rackmount servers would probably work well here.

If their 4.2J/GH number is correct, each chip is dissipating 1.3W. They aren't going to require anything special at all for cooling, likely small BGA heatsinks with pressure sensitive thermal adhesive would be fine.

Yeah, but if the chips remain stable at high clock rates while driving the voltage up, it'll need much better cooling. Also, its cheaper and saner to just use one large heatsink thats mounted on the board instead of placing the entire load on the chip itself.

95 chips = 30GH/s @ ~125W?

According to the pics posted on their website, BFL is using Al for their Little Single heatsink.

https://forums.butterflylabs.com/dbtgallery.php?do=view_image&id=1&gal=gallery

So they're using Aluminum for the Little Single, but Copper for the SC Single? https://forums.butterflylabs.com/dbtgallery.php?do=view_image&id=2&gal=gallery

That heatsink is a waste of money. Its clearly a high performance one, but you never waste copper on the fins on a heatpipe assembly, it doesn't improve the performance. Plus, the base isn't nickel plated. Even if I needed a low profile heatsink like that, thats not the one I'd be buying.

Plus, friedcat couldn't easily tile those closely due to the overlap of the heatpipe assembly, and the airflow is down facing on those thus also hard to use in small assemblies. Its easier to blow air across the board than straight into it. BFL keeps making this design mistake.

That's what the images Josh posted today suggest.

Actually i see no reason to reinvent the wheel here..
Either use the chips within a spec that requires no heatsink or use thermal epoxy to bond small commodity BGA RAM sinks to the chips and mount the PCBs in 5 1/4" 4-in-3 HDD cages that comes with standard 120mm fan.

Mount the cages in standard HDD or ATX tower cases(12 bays) and you could have 16 PCBs per case x 16 chips(at least) per PCB for a total of 256 chips per case. 256 x 1.3W = ~333Watt per case, perfect for a standard PC ATX style PSU.

Final throughput would conservatively be around 85Ghash per system. Servicing shouldn't be too much trouble either, it's all stock PC components.
If using a PC to control the PCBs, using 1 USB connector per PCB, it's within reach of most standard motherboards too. Can scale it up/down easily to get the best balance as needed.

BOM for each system:

HDD Tower case incl. 400W ATX PSU = ~$70-80
4 x HDD cages w/120mm fan= ~$60-75
256 x BGA heatsinks and Thermal epoxy = ~$30-40
ATX mobo + cpu + ram = $80-120 (Optionally customer installable, could be replaced with a USB hub to have single PC control multiple cases)
16 x usb cables = ~$15-20

So ~$300 in parts per COMPLETE system, which can be sourced MUCH cheaper in China, above prices are what they could be found for here in Euroland.

Examples:
HDD cage (http://www.amazon.com/Cooler-Master-Module-Device-STB-3T4-E3-GP/dp/B00129CDGC)(can be found much cheaper, just an example)
HDD Tower case  (http://www.span.com/product/9-Bay-5-25-Case-CF-5091-Silver-Steel-400W-PSU,-6-2xPorts~26261) (12 & 13 bay versions available too)

I assume so. I'm just going off the publicly available information, so your guess is as good as mine.

Diablo, the small adhesive attached BGA heatsinks weigh almost nothing. They're not going to stress the chips.

But are they going to help? BGA cases are flip-chip; with chip substrate connected to the top of the case.

QFN packages don't flip the chip and actually have air between the top of the package and the chip, because they need to accommodate the bonding wires. They really want to be cooled through the bottom of the PCB because this is where they have the least thermal resistance and a biggest piece of metal: ground connection for the substrate.

They do, but I think you'll be fighting a difficult battle cooling them through the thermal pad depending on the board design. Given the massive number of chips, the density is probably going to be quite high to keep board size reasonable. Cooling through the ground plane only works well if there aren't 8 chips all around the one is question all dumping heat in as well. If they can manage to keep the bottom clean they could definitely use a back plate to help cool the board.

Most QFNs have epoxy from the top of the die to the top of the package. It might not be a great thermal interface, but given the very low power per chip it will still be able to help.

Obviously the biggest constraint is time-to-market or time-to-mine.

Wouldn't it be practical to keep all PCB layers clean under the ground paddles; use a hole punch to cut out the PCB epoxy under the chips and mount the real heatsink on the bottoms with copper washers/thermal spreaders? The tops would then just need a mechanical clamp.

I'm just brainstorming. I made a suggestion about 5 months ago about using power IC packages in this thread: https://bitcointalk.org/index.php?topic=91173.msg1062969#msg1062969 . friedcat responded then immediately deleted his response because it probably disclosed something NDA-embargoed.

Instead of cutting the PCB, place large exposed solder pads on both sides of the board, connected by lots of vias.  Then just mount the heatsink to the exposed pads on the underside, while the thermal interface on the bottoms of the QFN packages get soldered to the connected pads on the top side.

Submerge it in mineral oil, and circulate it directly onto the chip faces that have an epoxy-heat-sink on top, and a through-hole to a sunk-ground on the bottom.

Beyond that, you can still cool them from the top, with epoxy-heat-sink that is either segregated and vacuum-bonded to the surface, or a standard thermal setup with "spring-tension", that will not damage the package with massive torque-pressure. Yet, still allow the heat-expanding aluminum and board to slide as needed.

The spring tensions can be simple push-through "V" tabs, attached to the heat-sinks directly, pushed through slots in the pcb, between the actual chips along the center-line of the board. (Not at the edges of the heat-sink... You want a center-line so the least movement is centralized and pressure around the whole surface uses the other chips as "supporting" feet to rest-on.)