Block Erupter: Dedicated Mining ASIC Project (Open for Discussion)

[Carlton Banks]

@friedcat

Will you be testing the ASIC processor/board out on the bitcoin Testnet to demonstrate it's hashing power to the public prior to release?

[friedcat]

@friedcat

Will you be testing the ASIC processor/board out on the bitcoin Testnet to demonstrate it's hashing power to the public prior to release?

What in my mind has been directly mining on the main blockchain and relay it with the pictures of mining devices to the public. Would you please elaborate the advantages of doing it first on the testnet? Thanks.

[lame.duck]

Mining in the testnet with such a power would be some sort of posing (or if you want call it 'marketing').  12 Thash of mining power should have a noticable impact on global hashing power, even if a lot of GPU-miners  stops mining.

[DutchBrat]

I say let the numbers speak for themselves (i.e. the amount of BTC mined in the 1st 24hrs  )

No need for a testnet demonstration....

[Carlton Banks]

My apologies, I didn't make myself clear.

Your IPO terms/information in this thread states that you will mine with the initial batch of hardware produced. It is not inconceivable that some changes to the final device will take place between the first batch of boards and the batch that you actually deliver to retail customers. So, your performance photographs will be of what are effectively prototype devices, not of the retail device. Is this correct, or have I misunderstood your terms?

[Comepradz]

Hi, Lately I came across this page >> https://en.bitcoin.it/wiki/Hardfork_Wishlist#Major_structural_changes << and there's something I want to ask regarding this:

Switch to block hashing algorithm secure against block withholding attacks.

Will it possibly disrupt Block Erupter's algorithm?

[Lethos]

Hi, Lately I came across this page >> https://en.bitcoin.it/wiki/Hardfork_Wishlist#Major_structural_changes << and there's something I want to ask regarding this:

Switch to block hashing algorithm secure against block withholding attacks.

Will it possibly disrupt Block Erupter's algorithm?

It's mostly a Cryptographic changes, that would be an issue, but as long as it still uses SHA256, it should be possible to still use it, minor software (mining) changes needed could cope maybe?

[burger]

How is this project progressing now?

It would be nice to know if there is any performance or prower savings between 130nm and  65nm?

[mrb]

Hi everyone. Our team has just started a project of mining ASIC design & production. We believe it will be both profitable for us and good for the Bitcoin community if we fully work it out.

It is widely believed that the NRE cost of ASIC is very high, while the margin cost of mass ASIC production is very low. However, we happen to be in China, where the NRE cost is much more reasonable (~150k$ for 130nm, ~500k$ for 65nm, furthermore much less if you do a 1/N mask) than most people thought. And we are going to take well advantage of that.

Our approach is incremental in all aspects. We will set several milestones and see what will happen if we achieve each of them. The report on each stage will be posted here.

In the design stage, including both the front-end and the back-end, we are going to fund ourselves. When we are finally ready to turn our design into real chips, we will seek investments, possibly both inside and outside the Bitcoin world. The first batch of our ASIC will not be an end, and we are going to renew our technology with the evolution of the hardware industry, so we are going to make this project a long-term one. However, this thread is not for investment asking, but merely for discussion and our status report.

Open discussions (feel free to add more!)

1. Self mining .vs. Selling hashes .vs. Selling hardware

2. Warnings, e.g. what are the typical causes to a failed ASIC manufacturing

3. Approaches to get enough funding for production

(To be extended)

Status reports

July 18
We have had our IC design company registered at Shenzhen, China. The name of our company is "bitfountain"

We also have signed the confidential contract with the IC manufacturer and got the process library necessary for correct DC synthesis.

July 29

Front-end work done. Preliminary specification given.

August 2

More optimization and trade-offs applied. MH/J improved and Watt/mm^2 reduced at the cost of some chip area increase.

August 11

The pictures of our IC layer are revealed.

(Larger pictures: https://bitcointalk.org/index.php?topic=99497.msg1092138#msg1092138)

(To be extended)

Quoting for the record.

[friedcat]

Update

Chip Specification
Technology Summary:
  130 nm
  1 Ploy
  6 Metal
  1 Top Metal
  Logic Process
Core Voltage: 1.2 V
I/O Voltage: 3.3 V
Core Frequency: 335 MHz
Core Frequency Range: 255-378 MHz
PLL Multiplier: 28
Power Consumption: 4.2 J/GHash
Number of Pads: 40
  22 Data
  18 Power
Package Type: QFN40
Packaged Chip Size: 6 mm x 6 mm

Chip Interface
Data Pins (22 in total):

clk                    i
soft-reset             i
reset                  i
cs                     i
addr[6]                i
data[8]                i/o
w_valid                i
w_allow                o
r_allow                o
r_req                  i

Address Allocation:

0-31    writing midstate
32-43   writing data
44-47   reading nonce

[kaerf]

awesome! finally some real technical info from an ASICs producer.

[niko]

How reliable is the power consumption figure?

[friedcat]

How reliable is the power consumption figure?

It's the back-end simulation result with 1.2V and 335MHz.
It depends on the actual voltage (1.2 typical, over-voltage and under-voltage is OK), the frequency you set for the chips, and the how well each individual chip could perform (random factors when producing).

[lame.duck]

Isn't the big pad connected to GND (so the number of power pads should be 19)?

[nedbert9]

Update

...

Power Consumption: 4.2 J/GHash

...

Packaged Chip Size: 6 mm x 6 mm

As a past ASICMINER shareholder, for about an hour , I'm simply curious about the changes within the specifications.

If the wattage has been lowered to from ~8 to 4.2 and the package area reduced from an estimated 21mm sq to 6mm sq. can we assume that additional sacrifices in hashrate were made to accommodate the smaller package and reduce heat issues?

[friedcat]

Isn't the big pad connected to GND (so the number of power pads should be 19)?

Yes. Thanks for clarification. We use the standard QFN way to package.
So there's a big pad in the middle, making the total number of pads 19.

[friedcat]

Can we assume that additional sacrifices in hashrate were made to accommodate the smaller package and reduce heat issues?

Yes. We did sacrifice some hashrate per area, that is, hashrate per wafer. But the compromise is worth it, because the loss is not significant, and because we have gained much lower ir drop and much better power efficiency.

[flynn]

Core Frequency: 335 MHz
Core Frequency Range: 255-378 MHz

Do I understand this correctly if I conclude that one chip will mine @ 335MH/s  ? or 378MH/s if it's a good one ?

or is there more than one stack in each chip ?

[friedcat]

Core Frequency: 335 MHz
Core Frequency Range: 255-378 MHz

Do I understand this correctly if I conclude that one chip will mine @ 335MH/s  ? or 378MH/s if it's a good one ?

Yes.

255-378 MHz is the result of the back-end simulation under 1.2V. If you do an over-voltage, it will probably be significantly higher, but the stability is hard to say. Exactly how high a frequency we could push them to, could only be answered when the chips are out.

[flynn]

Core Frequency: 335 MHz
Core Frequency Range: 255-378 MHz

Do I understand this correctly if I conclude that one chip will mine @ 335MH/s  ? or 378MH/s if it's a good one ?

Yes.

255-378 MHz is the result of the back-end simulation under 1.2V. If you do an over-voltage, it will probably be significantly higher, but the stability is hard to say. Exactly how high a frequency we could push them to, could only be answered when the chips are out.

Did you plan to sell some ? In such case do you have a price grid yet ?