No idea, but I presume from the lack of update that the chips are still in limbo in the packaging facility (remember they didn't want to ship until the 13th).

ASICs halten 100°C aus. Die gehen nicht so schnell kaputt

What power supply do you plan to use for core powering?

When are you expecting them back?

yup - let's stick with the KISS principle pls

Nice looking boards, but might it be better to switch to SMT connectors to keep the back flatter?

so i've recieved my usb keys from friedcat, they work great! but they do get very very hot.. I had a gander and it seems there's a wafer of thermal material and then a solid 3(ish)mm metal plate and that's it for cooling. I've seen pictures around with passive radiators bolted on instead, is this something i should consider?

Are you ocing that thing? Can you post cgminer code to it? Is ti true that it can mine with 386Mh/s if properly cooled?

Look - what I think about capacitors... Right in your placement with cross-section and 2 layer PCB (assuming 1.6 mm height):

4.4 mm x 1.6 mm = 7 mm^2 current loop from capacitor to power.

if you put capacitor right below chip - it would be 1.6 x 1.6mm current loop area. Roughly almost 2.8 times better.

Can't say directly inductances involved - but I believe that inductance for 4.4 x 1.6 mm current loop of this kind to be like 1.5 - 4 nH

In case if you put below the chip capacitor - it will have 0.5 - 1.6 nH additional serial inductance.

But - IF YOU USE 4-layer PCB and top layerstack would have say 0.1 mm dielectric - then current loop area would be much much less!

I just don't know your layerstack, but have this in mind - that power and ground layers should be CLOSE to each other, otherwise (if that's 2-layer pcb) - capacitors could live only on BOTTOM. Or PCB should not be thick - distance between layers affects this much.

1. INCLK should be tied to power or ground in case if it is not connected to clock generator. Otherwise if it will be floating, especially near half-voltage - it will case spontaneous oscillations.
   Better to feed it with oscillator, but don't feed less than 100 Mhz, or feed MUCH less than 100 Mhz as you can find bad package resonance.

2. IOVDD is hanging. IOREF is IOVDD/2. should be 1.8V at most (dielectric will likely broke at 2.5 V).

3. OUTCLK is likely would be difficult to send 'off-board', but at least it should be accessible as test-pin, to check if internal oscillator is running.

4. Can you give me gerbers and materials information - I'll check it with tools ?
I need from you layer stack description (i.e. I expect that this is FR4 and 1.6 mm board). I think that's too thick and better to have it thinner, if possible on 0.5 mm at most... but I would like to check.
Also I think that it could need different set of capacitors including smaller ( 0402 ) ones. I would like to check |Z| and see if it is fine or not.

Please give me part number of capacitor that you intended to place there (that say you intially have).

PS. And please treat chips with care - ESD properties are not known!

Should not be tolerant according to specs, oxide thickness is good for 2.0 V for long period.. Although it may tolerate 2.5V as well or even 3.3V - that's not recommended by foundry.

There's also ESD-protection diodes that will open and deliver current to IOVDD pin in this case - their Vth is about 0.6-0.7 V.

So if IOVDD is about 1.2 or 1.4 V - then it's safe! If higher - performance and reliability may vary.

And reading through your posts in this thread I can tell you really know your stuff.  Very much the opposite of BFL.

Also don't forget about level shifters - i/O is 1.8 V not 3.3 V (!!!).

1. INCLK should be tied to power or ground in case if it is not connected to clock generator. Otherwise if it will be floating, especially near half-voltage - it will case spontaneous oscillations.
   Better to feed it with oscillator, but don't feed less than 100 Mhz, or feed MUCH less than 100 Mhz as you can find bad package resonance.

Single chips is quick & dirty. Yes I want more - ideally I would like to see board that is powered with 12 V strings and have no external components (costs) except chips and passive components.
But that won't be simple to get. But that's what I was aiming to actually blow off any other component vendors from bill of materials and do not make bottlenecks with turn-around-times and such with inductors, many power regulators and such.
But this is what again - likely can't be done quicky, only if very lucky and there should be no complex filtering/anti-resonance issue between chips in a string (you see - we now connect CMMINUS, CMQ, CMPLUS to GND).

Trying to get my head around the protocol now, questions will come later.

Intron,

try an image hosting site like imgur.com

UPDATE: looking at the pad diagram, it looks to me like IOVDD is to send a logical 1 back as output (1.8V), and logical 0 output is GND.