Planned to use a 12V input, adjustable output voltage
DC/DC module that is capable of delivering up to 50 A
output current.
Not planning on designing such a power supply now,
would take too much time and effort I think. Or to speak
with Bob Pease: or you'll end up with just plain explosions:-)
intron
I was planning on using a similar style board to what you designed because I don't think the test sockets I've got will handle the clean, but intense power spikes posted previously by bitfury. Was planning on using an FTDI breakout module I have laying around for comms. 3.3V to 1.8V level shifting using resistors shouldn't be a problem, however I've also got a number of level shifter ICs at disposal if higher frequencies are required. For power I was going to use a 0-30V 0-20A lab psu and doing layout on a board that can jumper between 0.6-0.9V in 0.1V increments based on the LM2743.
To summarize my thoughts/process with regards to testing:
1) Reflow board with bitfury chip, decoupling caps, level shifters, attach copper shims to back of QFN48 mount location, attach LGA775 heatsink (modded with thermocouple mount)
2) Hook up lab PSU on 0.7V, max 10A
3) Attach function generator inclk generating 100mhz, use oscope to calibrate rise/fall such that dst pin has clean clock. May substitute FPGA in place of function generator depending on circumstances encountered. Higher frequencies will be tested dependent on the limitations of impedance correction of the tektronix clock generator and/or FPGA. I would guess that 400mhz off of the clock generator wouldn't be a problem and 180mhz off of the FPGA (Cyclone IV) would not.
4) Attach FTDI chip to SPI outs and test chip (repeat as necessary, also need info as to register layout of chip)
5) Wire inclk to ground, rerun tests while monitoring outclk with oscope. Mark chips with failed internal oscillators
6) Test remaining chips running on internal oscillators.
7) Rerun tests in 0.1V increments between 0.6-0.9V skipping 0.7V (already tested), recording power consumption/hashrate/temp.
Rerun tests with LM2743 psu (approx 90% efficient), recording power consumption/hashrate/temp.
9) Rerun tests with a chain of boards.
So at this point, the questions I have are:
1) Is this process satisfactory to what you're requesting?
2) Has anyone done the calculations on decoupling caps yet? One could go overcompensate but this would effect power/hashrate and thermal properties. I could figure it out and run simulations, but if someone has already done this....
3) I'm working out a test suite for the chips (and subsequent support for cgminer), using an FPGA as a dummy ASIC, however still need register addresses, etc.
I'm planning on doing the PCB on < 0.04" thick 2-oz FR-4, which we don't have any in stock, so going to pick some up when out running errands. Also was thinking may plate for longer when doing the vias to add some additional copper mass to spread heat.
-Ultrix
