I have collected together a set of pictures of all the S5 hash board revisions I can find, may or not be complete, but it's enough to be getting on with. Here are the pictures along with my initial comments on the changes. There will at this stage almost certainly be errors & omissions, this has all been done in a quite short period of time.
V1.1 2014-12-03First release. Easily identified by the large cleared copper areas.
VDD decoupling components on the front of the board
Only 5 of the 6 possible level shifters placed
16 Pin connector to controller board
PCI-e 6 pin power connectors close together in S3 compatible position
Single oscillator module Y1 on the ground level chip.
Credit to dogie for a decent high res pictures, wish the others were as good.
V1.3 2014-12-15Move to 18 pin connector to controller board. (Have not investigated what the additional signals are for?)
PCI-e 6 pin Power connector spacing widened, not S3 case compatible any more.
All 6 level shifters fitted along with additional SMT chip marked G07F. I think this is a SN74LVCG07 Buffer / Driver chip. Possibly / probably associated with the additional data connections from the Controller board?
Single oscillator module Y1 on the ground level chip.
V1.5 2014-12-20No immediately obvious difference to V1.3 but have not examined that closely.
V1.7 2014-12-22VDD decoupling components moved to reverse of the board. I have assumed they have been moved to the reverse as I do not have a picture of that side of the board.
The cleared copper area on the reverse of the chips is now a clear rectangle. I could guess clearing the way to easily fit a mini heatsink that comes later.
V1.9 2015-01-08Board layout changed to make provision for additional oscillator modules. Y1 to Y5. See V1.91 for more info.
Also provision for Oscillator modules on all stages Y1 to Y16.
V1.91 2015-03-28Additional oscillator modules Y1 to Y5 fitted. The level shifting chain is broken at each of the points that an additional oscillators are fitted. Each oscillator drives 4 pairs of chips, and the last on in the chain 3 pairs.
Addition. The LDO regulators on all but the last stage are removed. Voltage for the IO & PLL is now taken directly from the Core Voltage of the stage above.
This is a significant change & means that the IO & PLL voltage will track up and down in proportion to the supply voltage. Also it might have been possible (Have not measured) in the earlier boards at lower supply voltages for the LDO, which took it's supply from the core voltage 3 stages up, to drop out of regulation.V1.91 2015-03-28 (With Mini Heatsinks)Another version of V1.91 built with mini heatsinks fitted. Look the same as the ones fitted to S5+, so perhaps a trial? Do not know why they, on all the ones I have seen, did not fit heatsink to U20 & U29?
So there are 2 "big" changes that have taken place. First was on the transition from V1.1 to V1.3.The 6th level shifter was brought into play along with it's Driver Chip. The change from 16 to 18 connections to the Controller Board and the other Controller board changes was also made at this time and may be associated with this?
This could be the key change, but have no way, at the moment, of confirming that. I suspect it is not, but it would still be useful to understand exactly what this change does?
The second change is the one I am putting my money on being the key enabler of lower voltage working. V1.9 of the PCB made provision for additional oscillators, at V1.91 they were fitted.
The Oscillator count goes from 1 to 5 and the oscillator level shifting chain is broken at each of the points that an additional oscillators are fitted. Each oscillator then drives 4 pairs of chips, and the last on in the chain 3 pairs.
This change is consistent with one of sidehack's theory's that some of the signals are not making their way through the chain if the voltage is too low.
There are also pads on the layout for an oscillator for every pair of chips Y1 to Y16. These additional Oscillators have a different pad layout to the fitted ones Y1 to Y5
My S5 is has the V1.91 with heatsinks and can definitely be undervolted as shown in my previous posts. Most of the testing was with the 20150415 Firmware, but over the last few days have been using 20150715 with no noticeable difference.
I want also to take a look at the LDO regulator(s) for the PLL Analog & Digital power. Silly thing is I can only find one. It's either staring me in the face, on the reverse of the board or not there? I am sure that sidehack could put me right here.
If this all works my favoured solution for powering would be a modified Server PSU. They mostly have provision for a small adjustment 11.7V - 12.7V. I think some can be adjusted more than this, perhaps you could jack the sense input up and reduce the voltage? If anyone already has a solution, or wants to take a look that would be great? I am not that keen on the additional complexity, cost & reduction in efficiency of an additional VRM.
More to come but I have now shared everything I know and if anyone else wants to pitch in trying versions or understanding the changes please do so and let us know what you find?
Rich