Guy Corem
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August 19, 2015, 01:00:01 PM |
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sajidfbi
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August 19, 2015, 01:10:05 PM |
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Sooo .... anyone noticed what the effect of this announcement has had on the bitcoin price today? ![](https://ip.bitcointalk.org/?u=http%3A%2F%2Fs16.postimg.org%2F5gl7z1gut%2FBTCChart1385.png&t=665&c=FGqEtSBn2x1tQA) It's not about this announcment, it's just because the WAR between Bitcoins Core and BitCoins TX (another Module of Bitcoins introduced with 8MB Blockchain instead of 1MB) So now the problem here's that one of BitCoins Core or BitCoins TX will take over in some time and rate would get stable ahead then, There's might a chance that BitCoins rate would drop even more during this war.
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pekatete
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August 19, 2015, 01:18:10 PM |
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It's not about this announcment, it's just because the WAR between Bitcoins Core and BitCoins TX (another Module of Bitcoins introduced with 8MB Blockchain instead of 1MB) So now the problem here's that one of BitCoins Core or BitCoins TX will take over in some time and rate would get stable ahead then, There's might a chance that BitCoins rate would drop even more during this war. Insightful ..... so then bitmain just let the news out to ride the crash rather than being wholly responsible for the drop. That'd make sense. Still, there is probably a good amount of the drop (even lack of bounce) factoring in the implications of the increased network hashrate that the new chip'd represent (as is the norm).
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BellWether
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August 19, 2015, 01:26:16 PM |
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There was a flash crash apparently. Someone sold 2.3M at Bitfinex.
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sidehack
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August 19, 2015, 01:42:08 PM |
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Maybe they're also hoping to steal some thunder from LK Group, who I understand are to announce their new gear intentions on the 20th - which for China would probably mean in about 12 hours.
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Starin
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August 19, 2015, 01:50:57 PM |
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Well, this is good news. But with this efficiency I doubt it will be suitable for home mining as the noise could be too much. It's good that we can mod s5 fans, I hope we'll have the same chance. I know the last thing Bitmain worries is the noise levels, but it could be cool if they just work on it a bit. ![Wink](https://bitcointalk.org/Smileys/default/wink.gif)
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jonnybravo0311
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August 19, 2015, 01:52:13 PM |
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Is LK announcing the smaller process die chips, or are they still sticking with the 28nm finfet? I swear I read somewhere LK was pushing 14nm. Ah yes... here's that thread: https://bitcointalk.org/index.php?topic=1033676.0
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Jonny's Pool - Mine with us and help us grow! Support a pool that supports Bitcoin, not a hardware manufacturer's pockets! No SPV cheats. No empty blocks.
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NotFuzzyWarm
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August 19, 2015, 02:51:52 PM |
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It's still 28nm ? Are we stuck at 28?!?
Get over it. By and large, the '14nm' tag has become a marketing tool much like IoT. There are few devices that can benefit from going there (mostly phones, tablets, etc.) and there are devices that just-don't-need-it. As I and others here have repeatedly said, node size is NOT a major factor for mining ASICs. Bitmains new chip just proved that existing mature and well understood node sizes such as 28 and even 20nm have lots of room for performance improvement vs using 16-14nm with its inherent risks, mask costs and poor chip yields.
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sidehack
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August 19, 2015, 02:53:35 PM |
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ASICMiner's BE300 proved eight months ago that there was still substantial room for improvement in 28nm.
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NotFuzzyWarm
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August 19, 2015, 03:47:18 PM Last edit: August 19, 2015, 04:58:40 PM by NotFuzzyWarm |
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<snip> What is all customized design solution ? it will be designed only for professional users ? Share your ideas here ..
It means that the entire logical and physical layouts are done from scratch without using pre-made IP blocks. Most semiconductor fabs have built up libraries of various logical functions to use in copy-paste design. The problem with using pre-made or 3rd-party IP blocks is that they are optimized to perform their specific function but not necessarily optimal when it come to working with other sections. Even worse is that they are stand alone islands that must be connected to each other and that leads to signal routing problems and performance hits from excessively long connections between the blocks. With full custom everything is done from scratch using pre-made IP as perhaps a guide to what needs to be done in each block but that is it. Given Bitmain's experience with their previous chips they know what the logical structures need to be, now it was just a matter of translating those structures into optimized pathways on silicon. All physical layout of the chips is done with point-1 being shortest possible connections inside of and between the various bits like memory, math processors, coms, etc. Shorten the internal connections and switching losses drop like a stone allowing faster speeds and/or lower power.
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ITOP (OP)
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August 19, 2015, 11:20:39 PM |
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http://www.itop-corp.com/asset/cache/__h64__/internal/logo.png<snip> What is all customized design solution ? it will be designed only for professional users ? Share your ideas here ..
It means that the entire logical and physical layouts are done from scratch without using pre-made IP blocks. Most semiconductor fabs have built up libraries of various logical functions to use in copy-paste design. The problem with using pre-made or 3rd-party IP blocks is that they are optimized to perform their specific function but not necessarily optimal when it come to working with other sections. Even worse is that they are stand alone islands that must be connected to each other and that leads to signal routing problems and performance hits from excessively long connections between the blocks. With full custom everything is done from scratch using pre-made IP as perhaps a guide to what needs to be done in each block but that is it. Given Bitmain's experience with their previous chips they know what the logical structures need to be, now it was just a matter of translating those structures into optimized pathways on silicon. All physical layout of the chips is done with point-1 being shortest possible connections inside of and between the various bits like memory, math processors, coms, etc. Shorten the internal connections and switching losses drop like a stone allowing faster speeds and/or lower power. Thank you very much for clear explaination . ![Smiley](https://bitcointalk.org/Smileys/default/smiley.gif)
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johnyj
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August 20, 2015, 12:39:33 AM |
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In need of new rigs, come on bitmain spondoolies, get some new fancy products for christmas! ![Cool](https://bitcointalk.org/Smileys/default/cool.gif)
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DavidBAL
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August 20, 2015, 09:42:39 PM |
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SFMiner
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August 20, 2015, 10:03:32 PM |
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Nice, I can't wait to get my hands on the S7! Congrats on the impressive power efficiency, even at 28nm.
Bitmain, is there any way you can adopt a lower airflow design on the S7, like the one used in the S1 and S3? The jet engine included with the S5 is a little too intense IMHO.
Looking forward to the specs!!
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sidehack
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August 20, 2015, 10:37:13 PM |
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Part of that would require going back below 400W power dissipation on those heatsinks, which guesses for the S7 put it at 500W again like the S5.
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italianMiner72
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August 23, 2015, 06:21:19 PM |
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Sooo .... anyone noticed what the effect of this announcement has had on the bitcoin price today? ![](https://ip.bitcointalk.org/?u=http%3A%2F%2Fs16.postimg.org%2F5gl7z1gut%2FBTCChart1385.png&t=665&c=FGqEtSBn2x1tQA) plz peka, explain better, why this news, has had as a result the fall in the price? ![Huh](https://bitcointalk.org/Smileys/default/huh.gif) really interested!!!
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hexafraction
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August 23, 2015, 07:11:17 PM |
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What is all customized design solution ? it will be designed only for professional users ? Share your ideas here ..
No, that's not what it means. It means that the chip's production and design was fully customized. Although I'm not aware of the exact details, I'd assume the actual design from the ground up was customized (either invoking an ASIC cell library or possibly not), and possibly the production process (although I doubt that more).
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Blockhunter
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August 23, 2015, 07:21:29 PM |
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What is all customized design solution ? it will be designed only for professional users ? Share your ideas here ..
No, that's not what it means. It means that the chip's production and design was fully customized. Although I'm not aware of the exact details, I'd assume the actual design from the ground up was customized (either invoking an ASIC cell library or possibly not), and possibly the production process (although I doubt that more). if they didn't use a library... Then this seems they would have very top engineering to produce possibly the most efficient path?
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hexafraction
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August 23, 2015, 07:27:57 PM |
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What is all customized design solution ? it will be designed only for professional users ? Share your ideas here ..
No, that's not what it means. It means that the chip's production and design was fully customized. Although I'm not aware of the exact details, I'd assume the actual design from the ground up was customized (either invoking an ASIC cell library or possibly not), and possibly the production process (although I doubt that more). if they didn't use a library... Then this seems they would have very top engineering to produce possibly the most efficient path? Well, it's not like they lay out the masks by hand. Either they automate the design of masks from RTL or HDL, or they invoke a cell library that the foundry supports, that contains elements that are used in the construction of this design (most likely just logic, some storage, some lookup tables, and some clocking elements)
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