Bitcoin Core calculator, can it be home brewed?

[AJRGale]

Since you can calculate it by hand (pencil and paper linky link)
So I've had the idea on making a bitcoin calculator from scratch, since ASIC companies make 100s or 1000s of the into their chips, I wanted to know what is required to make one. Basic idea was to slap some discrete logic together and have it calculate on the bitcoin network.

home brew CPU style yo!

The reason for this is to understand the hardware required to make a asic chip work, them maybe refine it, in the end, who knows, this may turn into another ASIC development.

Hell, link me to some original posts asking the same thing, i cant seem to find anything.. or im blind..

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[TheRealSteve]

Look up the algorithms, understand how they work, break them down into specific sections, figure out the logic - easypeasy! *cough*

One 'cheating' route would be to look at old FPGA implementations, e.g. https://github.com/fpgaminer/Open-Source-FPGA-Bitcoin-Miner

Slight word of warning: you will need a lot of components taking up a lot of space and making soldering a lot of unfun.  A common component is a 32bit addder, you'll probably want multiple of these.  Here's a single 8bit one using transistors:

[sidehack]

Even doing this out of 74xx logic would be pretty sexy. I'd run one.

[jstefanop]

Since you can calculate it by hand (pencil and paper linky link)
So I've had the idea on making a bitcoin calculator from scratch, since ASIC companies make 100s or 1000s of the into their chips, I wanted to know what is required to make one. Basic idea was to slap some discrete logic together and have it calculate on the bitcoin network.

home brew CPU style yo!

The reason for this is to understand the hardware required to make a asic chip work, them maybe refine it, in the end, who knows, this may turn into another ASIC development.

Hell, link me to some original posts asking the same thing, i cant seem to find anything.. or im blind..

There are plenty of CPU bitcoin "calculators" as you call it. You most likely don't even know this but bitcoin mining did start off on the CPU...oh and trust me you won't refine any ASIC better than the huge bitcoin companies pumping millions into ASIC dev :p

[AJRGale]

I haven’t abandon this idea, I've been reading on how to calculate sha256. the more I'm rubbing my brain into it the more its picking up.. Step 1, almost complete! 1000 odd steps remaining! Yeah!

Also, here is something interesting: Sha256 on Spreadsheet in google docs.

And: PDF on Hardware Implementation of SHA-1 and SHA-2 Hash Functions.

in the other side of life, my laptop doesn't like having 16GB up its cloaca.. memtest+ dies, ubuntu goes in kernel panic if the sticks are the wrong way around.. anyway..

[sloopy]

I haven’t abandon this idea, I've been reading on how to calculate sha256. the more I'm rubbing my brain into it the more its picking up.. Step 1, almost complete! 1000 odd steps remaining! Yeah!

Also, here is something interesting: Sha256 on Spreadsheet in google docs.

And: PDF on Hardware Implementation of SHA-1 and SHA-2 Hash Functions.

in the other side of life, my laptop doesn't like having 16GB up its cloaca.. memtest+ dies, ubuntu goes in kernel panic if the sticks are the wrong way around.. anyway..

I gotta ask:
1. Did you start making the giant breadboard yet?
B. Did you try the ram in a different PC / Laptop to prove it is OK?
3. I hope you do this and make that giant thing. You should do a charity auction afterwards. Or, put it all to mine to an address for a charity. I bet there are plenty of collectors, and normal people (like me)who would bid something on it as an art piece.

[bmoscato]

This is a cool idea.

[2112]

Even doing this out of 74xx logic would be pretty sexy. I'd run one.

And how would you interface it with a computer with a network interface? I mean without using more TTL chips for the interface than for the computation core?

[AJRGale]

Even doing this out of 74xx logic would be pretty sexy. I'd run one.

And how would you interface it with a computer with a network interface? I mean without using more TTL chips for the interface than for the computation core?

same way when you interface with any other micro-controller, Serial baby!

I haven’t abandon this idea, I've been reading on how to calculate sha256. the more I'm rubbing my brain into it the more its picking up.. Step 1, almost complete! 1000 odd steps remaining! Yeah!

Also, here is something interesting: Sha256 on Spreadsheet in google docs.

And: PDF on Hardware Implementation of SHA-1 and SHA-2 Hash Functions.

in the other side of life, my laptop doesn't like having 16GB up its cloaca.. memtest+ dies, ubuntu goes in kernel panic if the sticks are the wrong way around.. anyway..

I gotta ask:
1. Did you start making the giant breadboard yet?
B. Did you try the ram in a different PC / Laptop to prove it is OK?
3. I hope you do this and make that giant thing. You should do a charity auction afterwards. Or, put it all to mine to an address for a charity. I bet there are plenty of collectors, and normal people (like me)who would bid something on it as an art piece.

1: that about step 250..

B: yeah, swapped memory into another 2 generation core i3 system, did the same thing, popped it into a 1st gen core i7 system, ran with out a hiccup ..
(also did the stick 1 to slot A/B, stick 2 to A/B, etc it looks like this memory controller doesn't like anything more then 4GB/slot)

III: I bet it would be big, since a 16bit CPU done that way takes up so much room (for example). but the idea is for educational understanding. so selling/donating it, maybe see what happens.

[sidehack]

Anything conceptually wrong with a discrete-logic SHA engine attached to a cheap micro with serial interface? Or should we make the brains out of logic too? A limited serial protocol should be deterministic, so the rest could be a state machine. UART it into something running cgminer and it'd be no different than any USB-tethered ASIC. I mean, except for the obvious.

Novak and I have talked for years about building a discrete-components simple 4- or 8-bit processor.

[2112]

You all guys deserve an F for your TTL logic design proposals involving serial interfaces.

Y'all need to hit the books and get a refresher on why all early computer interfaces were parallel: printers, disk drives, floppies, everything had wide cables: ribbons or Centronics or other SCSI connectors.

The serial interface revolution was made possible only by the cheap LSI ICs.

I don't remember Intel part numbers off hand, but go lookup the early Zilog parts from the Z80 family: PIO vs. SIO. And those were 8-bit parts. You will need at least 32-bit wide interfaces to sensibly implement in TTL the key component of SHA-256: 32-bit carry-look-ahead adder using 74181 and 74182, which are 4-bit slice parts.

[sidehack]

Sorry us amateurs aren't logic wizards with decades of experience. A lot of the folks on these forums have been in tech longer than I've been alive. I haven't done a lot with logic or controller design since about my fourth year of college, which for me was in the middle. I spent my six years getting three degrees and two minors so no real specialization in any one area like that.

Serial's easy to tie into a controller that actually exists today. My first thought was to immediately shift the data into sequential byte registers and work on it from there. Approximately a conversion from serial to parallel without requiring your controller to have a parallel IO interface, and pretty easy (well, comparatively) to implement with a shift register and some addressing. Or if you didn't want to consider it a part of your device, use an off-the-shelf converter chip to take USB (or whatever your controller uses) out to a parallel bus directly I reckon, but that feels more like cheating even if it really isn't.

I've got a Zilog Z80 in a drawer somewhere. I also have not looked at anything related to the innards of SHA256.

[2112]

The whole point is that rolled (not-unrolled) SHA-256 will require less gates than the serializer plus deserializer and the sequencers required to interface with anything less than 32-bit wide.

SHA-256 is essentially a 16-position shift register that is 32-bit wide. The fancy hashing feedback is mostly 32-bit wide adders and some bit twiddling that in hardware can be implemented mostly with wires and very few gates.

The above 32-bit circuit will be trivial to interface to the computer provided that  the computer has a 32-bit bus like EISA or PCI-X.

With any narrower bus more gates will go into the required sequencing logic than into the actual hash computation.

Show me any USB chip that can put-out or latch-in 32 bits in parallel.

All this doesn't require decades of engineering experience. Even completely cursory understanding of the evolution of the PC-compatible computers is sufficient to understand that the wide ribbon cables and long edge connectors disappeared from the computers only very recently. In the TTL days of SSI/MSI chips all interfaces were parallel and as wide as people could afford.

[AJRGale]

The whole point is that rolled (not-unrolled) SHA-256 will require less gates than the serializer plus deserializer and the sequencers required to interface with anything less than 32-bit wide.

SHA-256 is essentially a 16-position shift register that is 32-bit wide. The fancy hashing feedback is mostly 32-bit wide adders and some bit twiddling that in hardware can be implemented mostly with wires and very few gates.

The above 32-bit circuit will be trivial to interface to the computer provided that  the computer has a 32-bit bus like EISA or PCI-X.

With any narrower bus more gates will go into the required sequencing logic than into the actual hash computation.

Show me any USB chip that can put-out or latch-in 32 bits in parallel.

All this doesn't require decades of engineering experience. Even completely cursory understanding of the evolution of the PC-compatible computers is sufficient to understand that the wide ribbon cables and long edge connectors disappeared from the computers only very recently. In the TTL days of SSI/MSI chips all interfaces were parallel and as wide as people could afford.

im glad you know how these work, you could basically lay it out what logic is required to do what calculation..

 "bit twiddling that in hardware can be implemented mostly with wires and very few gates."
so 2 or 3 gates and wires will calculate square root, drop the whole numbers, shift up and then convert the decimal to hex, of first 8 prime numbers?
if you say yes, show me a boolean logic layout.

Really, if you going to come here to belittle us, bugger off. Simple.

I want to know how these things work, I'm a visual learner, and hell, if it is possible to make them, why the hell not? common, GBG made a NES mine bitcoins.. why cant I make a handful of transistors do it? or even out of 7400 series ttl chips..

[2112]

im glad you know how these work, you could basically lay it out what logic is required to do what calculation..

 "bit twiddling that in hardware can be implemented mostly with wires and very few gates."
so 2 or 3 gates and wires will calculate square root, drop the whole numbers, shift up and then convert the decimal to hex, of first 8 prime numbers?
if you say yes, show me a boolean logic layout.

Really, if you going to come here to belittle us, bugger off. Simple.

I want to know how these things work, I'm a visual learner, and hell, if it is possible to make them, why the hell not? common, GBG made a NES mine bitcoins.. why cant I make a handful of transistors do it? or even out of 7400 series ttl chips..

I don't know what your psychological disability is, so I can't help you.

The information required to solve all the technical problems to implement hardware SHA-256 miner is all available here on this board. Multiple people did their own implementation using the sensible learning technology of the XXI century: FPGA development kit. It takes between a week or a month to do it from scratch, depending on the student's aptitude. Simple FPGA development kits cost less than $100, many schools can get them for free.

For the problem you posed I think you misunderstood the description of Ki constants in the FIPS-180. FIPS describes how to derive them to show that those are "nothing-up-my-sleeve" numbers. Any hardware implementation will simply store those constants in ROM or other storage device.

[sidehack]

Thanks for your input on the logic of SHA256. Like I said, I haven't looked at it at all so I have no idea yet what the complexity is. AJR's fixin' to build this thing, I'm mostly just watching because I already have enough on my plate to keep me busy 80 hours a week.

If I were building it, I'd build it to interface to a computer built in the last 10 or 15 years. I have some machines with PCI-X, not sure I have anything with ISA anymore though. I know parallel is disappearing, which is why I had to whip out a Promise card to tie my optical drives in when I had to do a motherboard upgrade last year. It's the very fact that parallel busses are disappearing that I figured working a common serial bus into something usable by the logic would make it a heck of a lot easier to interface to a machine that anyone would still be running.

[2112]

Thanks for your input on the logic of SHA256. Like I said, I haven't looked at it at all so I have no idea yet what the complexity is. AJR's fixin' to build this thing, I'm mostly just watching because I already have enough on my plate to keep me busy 80 hours a week.

If I were building it, I'd build it to interface to a computer built in the last 10 or 15 years. I have some machines with PCI-X, not sure I have anything with ISA anymore though. I know parallel is disappearing, which is why I had to whip out a Promise card to tie my optical drives in when I had to do a motherboard upgrade last year. It's the very fact that parallel busses are disappearing that I figured working a common serial bus into something usable by the logic would make it a heck of a lot easier to interface to a machine that anyone would still be running.

It is EISA not ISA. The interface to the SHA-256 miner really wants to be 32-bit wide. As far as I know those are still being made as "passive backplane" industrial control computers. If somebody is dead-set on the TTL implementation EISA is the way to go because of sufficiently high IO voltages and sufficiently low IO clock speeds. I would think that meeting the PCI-X timing requirements using raw TTL logic may require some significant skills.

For the sane educational project probably the best kit would be something like http://zedboard.org/ which is Xilinx Zynq (ARM Cortex A9 & Kintex 7Artix 7^?  FPGA on the same chip with all the required interfaces).

For still sane but really budget-stressed project the $10 Cypress PSoC http://www.cypress.com/CY8CKIT-059 would be another sensible learning choice. It is ARM Cortex M3 with 24 CPLD-like Universal Digital Blocks. And the whole development toolchain for it is free from Cypress Semiconductor without the need to be affiliated with an educational institution.

In my opinion soldering 74-series chips by hand is a skill about as useful as knowledge of the railroad engineer on how to operate a steam locomotive. We have 21st century now. Search for "Xilinx ISE schematic capture" and get on with the program...

http://uhaweb.hartford.edu/kmhill/suppnotes/iseschem/index.htm
http://www.digilentinc.com/Data/Documents/Tutorials/Xilinx%20ISE%20WebPACK%20Schematic%20Capture%20Tutorial.pdf

Edit: grammar fixes

[sidehack]

All I'mma say is, steam locomotives are badass. Sure they don't have 3000HP 16-cylinder diesel engines with 700CID per cylinder, but if I were a train driver I'd want to know how to run them too. Punching logic into a capture and flashing it to an FPGA is really cool, but patching together PDIPs to do the same thing is a different kind of cool.

[2112]

All I'mma say is, steam locomotives are badass. Sure they don't have 3000HP 16-cylinder diesel engines with 700CID per cylinder, but if I were a train driver I'd want to know how to run them too. Punching logic into a capture and flashing it to an FPGA is really cool, but patching together PDIPs to do the same thing is a different kind of cool.

I have nothing against steam locomotives. But there are two kinds of steam locomotive engineers:

1) the ones that only know how to shovel the coal from the back tender to the front boiler;

2) the ones that could explain to you various kinds of https://en.wikipedia.org/wiki/Valve_gear and why https://en.wikipedia.org/wiki/Walschaerts_valve_gear is the most popular.

As a kid I was fascinated by the steam locomotives and had a good fortune of meeting the 2nd kind of railroad engineer.

It is the key difference between education and training and it has been known for a long time:

https://en.wikipedia.org/wiki/Hacker_koan#Enlightenment

A novice was trying to fix a broken Lisp machine by turning the power off and on.
Knight, seeing what the student was doing, spoke sternly: "You cannot fix a machine by just power-cycling it with no understanding of what is going wrong."
Knight turned the machine off and on.
The machine worked.

[sidehack]

I grew up surrounded by the kinds of people that could do both. Not literally for trains, but anything from telephone systems to tractors.