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 Author Topic: Why is Butterfly Labs so secretive?  (Read 6948 times)
bitmar
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 October 14, 2012, 03:59:11 PM

You bring that table to attempt to prove your point, then find out it proves you wrong, so you retract it saying it is old and does not apply anymore?

The observation I made from this table is still valid to this day. I was comparing one of its 180nm ASIC with a 120nm Virtex 2 FPGA (180/120 = 1.5x feature scale difference). Today, you would be comparing a 65nm ASIC (presumed process node for BFL ASIC) against the 45nm FPGAs that all other Bitcoin mining vendor use (Spartan6 LX150), that's a 65/45 = 1.4x feature scale difference. So in both cases the power efficiency of FPGAs over the ASICs (that I am comparing them with) is the same, because power efficiency is directly inversely proportional to the square of the feature size.

One more time: please put your money where you mouth is if you are so convinced of yourself: http://betsofbitco.in/item?id=665

You trying to say that a typical 65nm ASIC is "several times faster" than a typical 45nm FPGA? what order of magnitude is the difference? I think many of us are interesting your observation. Do you know what is avarage costs of production  65nm ASIC?

"You bring that table to attempt to prove your point, then find out it proves you wrong, so you retract it saying it is old and does not apply anymore?  "
See how I signed table

You do not proved anything except that ASIC is more energy efficient. I know it. Conversation is whether ASIC can be "several times faster" than a similar FPGA.

FFS: http://en.wikipedia.org/wiki/Field-programmable_gate_array
"Historically, FPGAs have been slower, less energy efficient and generally achieved less functionality than their fixed ASIC counterparts. A study has shown that designs implemented on FPGAs need on average 40 times as much area, draw 12 times as much dynamic power, and are three times slower than the corresponding ASIC implementations.[22]"

40 times less area * 3 times faster = 120x at the same process node

It's really simple guys, every logic block and interconnect needs a bunch of transistors to control them, but on ASIC you just lay the circuit down as you want it to run. Because of this you have far more transistors actually performing the work rather than controlling internal functions.

So even though the underlying features are the same at a given process node, FPGA suffers a disadvantage in area and speed, but makes up for it with flexibility. ASIC is locked in function, but very, very fast at execution.

OMG !
These data are historical, now the difference is less because the FPGA is growing faster than ASIC. FPGA technology is more advanced and more popular than ASIC. These are not my words, but experts in the field. ASIC technology has great potential but is very expensive and very risky
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mrb
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 October 14, 2012, 08:08:59 PM

FFS: http://en.wikipedia.org/wiki/Field-programmable_gate_array
"Historically, FPGAs have been slower, less energy efficient and generally achieved less functionality than their fixed ASIC counterparts. A study has shown that designs implemented on FPGAs need on average 40 times as much area, draw 12 times as much dynamic power, and are three times slower than the corresponding ASIC implementations.[22]"

40 times less area * 3 times faster = 120x at the same process node

It's really simple guys, every logic block and interconnect needs a bunch of transistors to control them, but on ASIC you just lay the circuit down as you want it to run. Because of this you have far more transistors actually performing the work rather than controlling internal functions.

So even though the underlying features are the same at a given process node, FPGA suffers a disadvantage in area and speed, but makes up for it with flexibility. ASIC is locked in function, but very, very fast at execution.

OMG !
These data are historical, now the difference is less because the FPGA is growing faster than ASIC. FPGA technology is more advanced and more popular than ASIC. These are not my words, but experts in the field.

No, FPGAs are not more advanced. The best technology for both FPGAs and ASICs is 28nm today. I would love to hear a quote from your "experts". I could help you clarify how you misunderstand their words.

You do not proved anything except that ASIC is more energy efficient. I know it. Conversation is whether ASIC can be "several times faster" than a similar FPGA.

You are one centimeter away from understanding my point. Let me try it this way. If you know that ASICs are more power efficient, that means they do more work per Joule (or per Watt if that makes it easier for you to understand). Therefore, when comparing a 10 Watt ASIC chip to a 10 Watt FPGA chip, you can guess the ASIC chip will accomplish more work, right? So if an ASIC is 100x more power efficient than an FPGA, the 10 Watt ASIC chip will perform 100x more work than the 10 Watt FPGA chip. In other words it will be 100x faster. That's it.
bitmar
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 October 14, 2012, 09:23:45 PM

FFS: http://en.wikipedia.org/wiki/Field-programmable_gate_array
"Historically, FPGAs have been slower, less energy efficient and generally achieved less functionality than their fixed ASIC counterparts. A study has shown that designs implemented on FPGAs need on average 40 times as much area, draw 12 times as much dynamic power, and are three times slower than the corresponding ASIC implementations.[22]"

40 times less area * 3 times faster = 120x at the same process node

It's really simple guys, every logic block and interconnect needs a bunch of transistors to control them, but on ASIC you just lay the circuit down as you want it to run. Because of this you have far more transistors actually performing the work rather than controlling internal functions.

So even though the underlying features are the same at a given process node, FPGA suffers a disadvantage in area and speed, but makes up for it with flexibility. ASIC is locked in function, but very, very fast at execution.

OMG !
These data are historical, now the difference is less because the FPGA is growing faster than ASIC. FPGA technology is more advanced and more popular than ASIC. These are not my words, but experts in the field.

No, FPGAs are not more advanced. The best technology for both FPGAs and ASICs is 28nm today. I would love to hear a quote from your "experts". I could help you clarify how you misunderstand their words.

You do not proved anything except that ASIC is more energy efficient. I know it. Conversation is whether ASIC can be "several times faster" than a similar FPGA.

You are one centimeter away from understanding my point. Let me try it this way. If you know that ASICs are more power efficient, that means they do more work per Joule (or per Watt if that makes it easier for you to understand). Therefore, when comparing a 10 Watt ASIC chip to a 10 Watt FPGA chip, you can guess the ASIC chip will accomplish more work, right? So if an ASIC is 100x more power efficient than an FPGA, the 10 Watt ASIC chip will perform 100x more work than the 10 Watt FPGA chip. In other words it will be 100x faster. That's it.

I do not want to talk about the obvious and fundamental. You just lost all credibility. This conversation does not make sense.  Not at this level.
It is obvious that you can do ASIC 100x faster than  FPGA and can do FPGA 100x faster than ASIC. Not the point. The conversation is about the real possibility of the implementation of ASIC several times faster than the current leading FPGA chips (like Artix-7, Kintex-7,Virtex-7,Spartan-6), having a small budget. Do you know a company that did it? I not found any example.
mrb
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 October 14, 2012, 10:25:23 PM

I do not want to talk about the obvious and fundamental. You just lost all credibility. This conversation does not make sense.  Not at this level.
It is obvious that you can do ASIC 100x faster than  FPGA and can do FPGA 100x faster than ASIC. Not the point. The conversation is about the real possibility of the implementation of ASIC several times faster than the current leading FPGA chips (like Artix-7, Kintex-7,Virtex-7,Spartan-6), having a small budget. Do you know a company that did it? I not found any example.

Yes! The table you quoted was showing multiple ASIC implementations from multiple companies that significantly outperformed FPGAs. You rejected that argument, thinking one cannot replicate a small ~300MHz logic unit (20k gates) many times across the die area, but I pointed out to you this is possible by giving the example of a CPU with 10+ million gates running at 500MHz. Then you buried your head into the sand saying "Do not compare CPU with ASIC". A CPU is an ASIC. Maybe a better example to convince you would be to talk a GPU, where shaders occupy most of the die area and are precisely that: a small logic unit replicated many times across the die area.

Perhaps another way to show it to you is as is. In your table:

• The FPGA in [16] has a die size of 317 mm^2. Most of the space is occupied by slices, but let's be really conservative and say only half the die area is occupied by slices, or 150 mm^2. So they did 1Gbps by utilizing about 30 mm^2 of the die area (150 mm^2 * 2120 slices / 10752 total slices on the chip.)
• On the other hand the ASIC in [21] which I managed to track down was a reference to http://www.cast-inc.com/ip-cores/encryption/sha-256/cast_sha256.pdf is a SHA-256 core doing 2Gbps by utilizing only 0.25 mm^2 (PDF says exactly 250040 um^2).

So, obviously the chip doing twice the work in 1/120th the die space provides a building block that can be utilized to make a full-size chip that significantly outperforms FPGAs. Don't say again that "FPGAs progressed faster than ASICs", this is not true I have already pointed out that they both top out at 28nm today, so the comparison of FPGAs vs. ASICs made at the time your table was composed is still valid today.

Also I already showed here: https://bitcointalk.org/index.php?topic=95762.0  that manufacturing at 65nm costs only \$500k which is clearly within reach of BFL's financial resources.
bobitza
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 October 14, 2012, 10:51:12 PM

Jeez, dont you have pms?

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Bogart
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 October 14, 2012, 10:55:08 PM

Is the die feature size something that can be easily checked on a production chip?

Could someone just open a chip's casing, look at the die with a microscope, and say "oh, that's 130nm", etc?

Or is this size below the limit of what's observable optically without being limited by diffraction, and would require a SEM or somesuch to "see"?

"All safe deposit boxes in banks or financial institutions have been sealed... and may only be opened in the presence of an agent of the I.R.S." - President F.D. Roosevelt, 1933
squid
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 October 14, 2012, 11:24:03 PM

I do not want to talk about the obvious and fundamental. You just lost all credibility. This conversation does not make sense.  Not at this level.
It is obvious that you can do ASIC 100x faster than  FPGA and can do FPGA 100x faster than ASIC. Not the point. The conversation is about the real possibility of the implementation of ASIC several times faster than the current leading FPGA chips (like Artix-7, Kintex-7,Virtex-7,Spartan-6), having a small budget. Do you know a company that did it? I not found any example.

Yes! The table you quoted was showing multiple ASIC implementations from multiple companies that significantly outperformed FPGAs. You rejected that argument, thinking one cannot replicate a small ~300MHz logic unit (20k gates) many times across the die area, but I pointed out to you this is possible by giving the example of a CPU with 10+ million gates running at 500MHz. Then you buried your head into the sand saying "Do not compare CPU with ASIC". A CPU is an ASIC. Maybe a better example to convince you would be to talk a GPU, where shaders occupy most of the die area and are precisely that: a small logic unit replicated many times across the die area.

Perhaps another way to show it to you is as is. In your table:

• The FPGA in [16] has a die size of 317 mm^2. Most of the space is occupied by slices, but let's be really conservative and say only half the die area is occupied by slices, or 150 mm^2. So they did 1Gbps by utilizing about 30 mm^2 of the die area (150 mm^2 * 2120 slices / 10752 total slices on the chip.)
• On the other hand the ASIC in [21] which I managed to track down was a reference to http://www.cast-inc.com/ip-cores/encryption/sha-256/cast_sha256.pdf is a SHA-256 core doing 2Gbps by utilizing only 0.25 mm^2 (PDF says exactly 250040 um^2).

So, obviously the chip doing twice the work in 1/120th the die space provides a building block that can be utilized to make a full-size chip that significantly outperforms FPGAs. Don't say again that "FPGAs progressed faster than ASICs", this is not true I have already pointed out that they both top out at 28nm today, so the comparison of FPGAs vs. ASICs made at the time your table was composed is still valid today.

Also I already showed here: https://bitcointalk.org/index.php?topic=95762.0  that manufacturing at 65nm costs only \$500k which is clearly within reach of BFL's financial resources.

If BFL had 65 nm process they would be talking about it since that would probably be smaller than any competitors, its this secrecy that makes me think they are starting with the largest die size. The other reason to start with largest die size is because you then have ways to continue selling asics in the future. For example, a year after their first asic sells, they can they say cell 65 or 90 nm.. then after that go even smaller. This would give their business longevity and room to grow, while maximizing profits.
scrybe
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 October 15, 2012, 08:19:31 AM

You bring that table to attempt to prove your point, then find out it proves you wrong, so you retract it saying it is old and does not apply anymore?

The observation I made from this table is still valid to this day. I was comparing one of its 180nm ASIC with a 120nm Virtex 2 FPGA (180/120 = 1.5x feature scale difference). Today, you would be comparing a 65nm ASIC (presumed process node for BFL ASIC) against the 45nm FPGAs that all other Bitcoin mining vendor use (Spartan6 LX150), that's a 65/45 = 1.4x feature scale difference. So in both cases the power efficiency of FPGAs over the ASICs (that I am comparing them with) is the same, because power efficiency is directly inversely proportional to the square of the feature size.

One more time: please put your money where you mouth is if you are so convinced of yourself: http://betsofbitco.in/item?id=665

You trying to say that a typical 65nm ASIC is "several times faster" than a typical 45nm FPGA? what order of magnitude is the difference? I think many of us are interesting your observation. Do you know what is avarage costs of production  65nm ASIC?

"You bring that table to attempt to prove your point, then find out it proves you wrong, so you retract it saying it is old and does not apply anymore?  "
See how I signed table

You do not proved anything except that ASIC is more energy efficient. I know it. Conversation is whether ASIC can be "several times faster" than a similar FPGA.

FFS: http://en.wikipedia.org/wiki/Field-programmable_gate_array
"Historically, FPGAs have been slower, less energy efficient and generally achieved less functionality than their fixed ASIC counterparts. A study has shown that designs implemented on FPGAs need on average 40 times as much area, draw 12 times as much dynamic power, and are three times slower than the corresponding ASIC implementations.[22]"

40 times less area * 3 times faster = 120x at the same process node

It's really simple guys, every logic block and interconnect needs a bunch of transistors to control them, but on ASIC you just lay the circuit down as you want it to run. Because of this you have far more transistors actually performing the work rather than controlling internal functions.

So even though the underlying features are the same at a given process node, FPGA suffers a disadvantage in area and speed, but makes up for it with flexibility. ASIC is locked in function, but very, very fast at execution.

OMG !
These data are historical, now the difference is less because the FPGA is growing faster than ASIC. FPGA technology is more advanced and more popular than ASIC. These are not my words, but experts in the field. ASIC technology has great potential but is very expensive and very risky

Just because the underlying process technology changes does not mean that the ratio between logic and control in FPGA is less efficient than ASIC. I can find articles dating back to 2003 that claim that FPGA is faster than ASIC, but when it comes down to it they are talking about "typical" ASIC in order to allow Xilinx and Altera to look better.

more flexibility == needs more gates == less efficient == ASIC is better if you can afford to spin the silicon.

This is not in question is it? The Virtex 7 has 6.8 billion transistors, and can simulate an ASIC with up to ~20 million (24M in some reports) gates. This means that Xilinx is burning ~340 transistors per gate.

It's also \$30k each for that FPGA, but the same number of transistors from NVIDIA are in the GK110 (essentially a gigantic ASIC) for far less.

"...as simple as possible, but no simpler" -AE
Unacceptable
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 October 15, 2012, 10:07:18 AM

You bring that table to attempt to prove your point, then find out it proves you wrong, so you retract it saying it is old and does not apply anymore?

The observation I made from this table is still valid to this day. I was comparing one of its 180nm ASIC with a 120nm Virtex 2 FPGA (180/120 = 1.5x feature scale difference). Today, you would be comparing a 65nm ASIC (presumed process node for BFL ASIC) against the 45nm FPGAs that all other Bitcoin mining vendor use (Spartan6 LX150), that's a 65/45 = 1.4x feature scale difference. So in both cases the power efficiency of FPGAs over the ASICs (that I am comparing them with) is the same, because power efficiency is directly inversely proportional to the square of the feature size.

One more time: please put your money where you mouth is if you are so convinced of yourself: http://betsofbitco.in/item?id=665

You trying to say that a typical 65nm ASIC is "several times faster" than a typical 45nm FPGA? what order of magnitude is the difference? I think many of us are interesting your observation. Do you know what is avarage costs of production  65nm ASIC?

"You bring that table to attempt to prove your point, then find out it proves you wrong, so you retract it saying it is old and does not apply anymore?  "
See how I signed table

You do not proved anything except that ASIC is more energy efficient. I know it. Conversation is whether ASIC can be "several times faster" than a similar FPGA.

FFS: http://en.wikipedia.org/wiki/Field-programmable_gate_array
"Historically, FPGAs have been slower, less energy efficient and generally achieved less functionality than their fixed ASIC counterparts. A study has shown that designs implemented on FPGAs need on average 40 times as much area, draw 12 times as much dynamic power, and are three times slower than the corresponding ASIC implementations.[22]"

40 times less area * 3 times faster = 120x at the same process node

It's really simple guys, every logic block and interconnect needs a bunch of transistors to control them, but on ASIC you just lay the circuit down as you want it to run. Because of this you have far more transistors actually performing the work rather than controlling internal functions.

So even though the underlying features are the same at a given process node, FPGA suffers a disadvantage in area and speed, but makes up for it with flexibility. ASIC is locked in function, but very, very fast at execution.

OMG !
These data are historical, now the difference is less because the FPGA is growing faster than ASIC. FPGA technology is more advanced and more popular than ASIC. These are not my words, but experts in the field. ASIC technology has great potential but is very expensive and very risky

Just because the underlying process technology changes does not mean that the ratio between logic and control in FPGA is less efficient than ASIC. I can find articles dating back to 2003 that claim that FPGA is faster than ASIC, but when it comes down to it they are talking about "typical" ASIC in order to allow Xilinx and Altera to look better.

more flexibility == needs more gates == less efficient == ASIC is better if you can afford to spin the silicon.

This is not in question is it? The Virtex 7 has 6.8 billion transistors, and can simulate an ASIC with up to ~20 million (24M in some reports) gates. This means that Xilinx is burning ~340 transistors per gate.

It's also \$30k each for that FPGA, but the same number of transistors from NVIDIA are in the GK110 (essentially a gigantic ASIC) for far less.

Tι στo διάoλo είστε παιδιά μιλάμε.Xάσατε μoυ μετά την 3η θέση.H ελληνική όλα μoυ.

"If you run into an asshole in the morning, you ran into an asshole. If you run into assholes all day long, you are the asshole."  -Raylan Givens
"An ASIC being late is perfectly normal, predictable, and legal..."Hashfast & BFL slogan
bitmar
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 October 15, 2012, 04:53:37 PM

I do not want to talk about the obvious and fundamental. You just lost all credibility. This conversation does not make sense.  Not at this level.
It is obvious that you can do ASIC 100x faster than  FPGA and can do FPGA 100x faster than ASIC. Not the point. The conversation is about the real possibility of the implementation of ASIC several times faster than the current leading FPGA chips (like Artix-7, Kintex-7,Virtex-7,Spartan-6), having a small budget. Do you know a company that did it? I not found any example.

Yes! The table you quoted was showing multiple ASIC implementations from multiple companies that significantly outperformed FPGAs. You rejected that argument, thinking one cannot replicate a small ~300MHz logic unit (20k gates) many times across the die area, but I pointed out to you this is possible by giving the example of a CPU with 10+ million gates running at 500MHz. Then you buried your head into the sand saying "Do not compare CPU with ASIC". A CPU is an ASIC. Maybe a better example to convince you would be to talk a GPU, where shaders occupy most of the die area and are precisely that: a small logic unit replicated many times across the die area.

Perhaps another way to show it to you is as is. In your table:

• The FPGA in [16] has a die size of 317 mm^2. Most of the space is occupied by slices, but let's be really conservative and say only half the die area is occupied by slices, or 150 mm^2. So they did 1Gbps by utilizing about 30 mm^2 of the die area (150 mm^2 * 2120 slices / 10752 total slices on the chip.)
• On the other hand the ASIC in [21] which I managed to track down was a reference to http://www.cast-inc.com/ip-cores/encryption/sha-256/cast_sha256.pdf is a SHA-256 core doing 2Gbps by utilizing only 0.25 mm^2 (PDF says exactly 250040 um^2).

So, obviously the chip doing twice the work in 1/120th the die space provides a building block that can be utilized to make a full-size chip that significantly outperforms FPGAs. Don't say again that "FPGAs progressed faster than ASICs", this is not true I have already pointed out that they both top out at 28nm today, so the comparison of FPGAs vs. ASICs made at the time your table was composed is still valid today.

Also I already showed here: https://bitcointalk.org/index.php?topic=95762.0  that manufacturing at 65nm costs only \$500k which is clearly within reach of BFL's financial resources.

ok, I'm not going to argue who is right. I am not an expert in this field. I base on the press releases and offers of companies that produce ASIC. You Suggesting that  production of 65nm ASIC costs about \$ 500k from this thread (https://bitcointalk.org/index.php?topic=91173.msg1003326#msg1003326) -> only NRE costs.  Friedcat  is not authority for me.
BFL's offers us very high perfomance ASIC chip they must use the ASIC prototyping with multi-FPGA chip partitioning ( to 96 million gates max, without prototyping cost would be several times higher), it is not cheap,  500k\$ will cost only mask
As I wrote before there is no sense to continue this discussion in this forum. Maybe on some other forum someone will be able to answer.

scrybe
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 October 16, 2012, 02:14:10 AM

Tι στo διάoλo είστε παιδιά μιλάμε.Xάσατε μoυ μετά την 3η θέση.H ελληνική όλα μoυ.

What the hell are you children milame.Chasate after my third thesi.I all my Greek.

I still have no idea what it means, but I think I've been insulted.

Cheers!

"...as simple as possible, but no simpler" -AE
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 October 16, 2012, 03:32:50 AM

Tι στo διάoλo είστε παιδιά μιλάμε.Xάσατε μoυ μετά την 3η θέση.H ελληνική όλα μoυ.

What the hell are you children milame.Chasate after my third thesi.I all my Greek.

I still have no idea what it means, but I think I've been insulted.

Cheers!

Here is what was it meant to say:

"What the hell are you guys talking about.You lost me after the 3rd post.Its all greek to me."

If the translator didn't get it correct, I'm sorry

"If you run into an asshole in the morning, you ran into an asshole. If you run into assholes all day long, you are the asshole."  -Raylan Givens
"An ASIC being late is perfectly normal, predictable, and legal..."Hashfast & BFL slogan
scrybe
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 October 17, 2012, 03:25:51 AM

Tι στo διάoλo είστε παιδιά μιλάμε.Xάσατε μoυ μετά την 3η θέση.H ελληνική όλα μoυ.

What the hell are you children milame.Chasate after my third thesi.I all my Greek.

I still have no idea what it means, but I think I've been insulted.

Cheers!

Here is what was it meant to say:

"What the hell are you guys talking about.You lost me after the 3rd post.Its all greek to me."

If the translator didn't get it correct, I'm sorry

I love how much info there is available now about FPGA and ASIC technology. A few hours of reading and I've taken my geek to a whole new level. I'm even toying around with getting an FPGA to play with. Granted I do own a book by Jon Stokes...

No worries on the translator, our future robot overlords obviously have no long term plans for Greece.

"...as simple as possible, but no simpler" -AE
Unacceptable
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 October 17, 2012, 03:41:16 AM

Tι στo διάoλo είστε παιδιά μιλάμε.Xάσατε μoυ μετά την 3η θέση.H ελληνική όλα μoυ.

What the hell are you children milame.Chasate after my third thesi.I all my Greek.

I still have no idea what it means, but I think I've been insulted.

Cheers!

Here is what was it meant to say:

"What the hell are you guys talking about.You lost me after the 3rd post.Its all greek to me."

If the translator didn't get it correct, I'm sorry

I love how much info there is available now about FPGA and ASIC technology. A few hours of reading and I've taken my geek to a whole new level. I'm even toying around with getting an FPGA to play with. Granted I do own a book by Jon Stokes...

No worries on the translator, our future robot overlords obviously have no long term plans for Greece.

I used Bing to translate to greek

http://www.bing.com/translator/

See if it transalates back to what I really said

"If you run into an asshole in the morning, you ran into an asshole. If you run into assholes all day long, you are the asshole."  -Raylan Givens
"An ASIC being late is perfectly normal, predictable, and legal..."Hashfast & BFL slogan
scrybe
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 October 18, 2012, 03:07:50 AM

Quote
What the hell are you guys talking about. you lost me after the 3rd place all my Greek.

You used a colloquialism at the end that it didn't understand, but it did better at reversing itself than Google did.

"...as simple as possible, but no simpler" -AE
Unacceptable
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 October 18, 2012, 03:11:43 AM

Quote
What the hell are you guys talking about. you lost me after the 3rd place all my Greek.

You used a colloquialism at the end that it didn't understand, but it did better at reversing itself than Google did.

I've had much better luck with bing,than anyother translator for whatever reason

"If you run into an asshole in the morning, you ran into an asshole. If you run into assholes all day long, you are the asshole."  -Raylan Givens