Process-invariant hardware metric: hash-meters per second (η-factor)

[2112]

Avalon chip count and power usage are available. You can now update your comparison table.

Thanks, but I need the actual die measurements, not the number of chips-per-wafer.

Please let me know if/when they are posted by either the Avalon manufacturers (I'll take their word for it) or some third party (must include a photo).

That information was available since last year.

https://bitcointalk.org/index.php?topic=120184.msg1294431#msg1294431

Code:

TSMC
TMEM91
================================================
Chip Size :   X = 3.9760 ,Y = 4.0560 mm
Reticle Size :   X/cell =  3 ,Y/cell =  3
Offset Value :   X = -3.7668 ,Y = -2.2990 mm
Alignment Mark :   (118.80,83.20),(-118.80,-83.20)
Alignment Mark Tolerant Distance :      1.6 mm
Notch Reserved Distance :   7.75 mm
Start Distance :   7.75 mm
Ring Edge :   3.0 mm
Photo Die Number:    4055

[1715051994]

1715051994

[eldentyrell]

That information was available since last year.

Quite possible!  I can't keep up with the tangled mess of threads this forum has become…  Case in point, I cannot find Avalon's statement on the hashrate per chip.  If you can post a link to that I'll add them.

https://bitcointalk.org/index.php?topic=120184.msg1294431#msg1294431

That's weird, I wonder if he edited his post, the very next one is a post by me complaining that he posted the packaged size instead of the die size (in Oct 2012).

[eldentyrell]

(21-Jun) Oh my, this is terribly embarrassing.  When calculating the η-factor for bitfury last night I used the gate length instead of the feature size.  I have corrected this; please see above.  No wonder his numbers came out so high.

Any additional checking of my arithmetic would be welcome.

[eldentyrell]

That information was available since last year.

Quite possible!  I can't keep up with the tangled mess of threads this forum has become…  Case in point, I cannot find Avalon's statement on the hashrate per chip.  If you can post a link to that I'll add them.

I found a bunch of random third-party sites tossing around the figure of 282 (MH/s)/chip.  If somebody can post a link to someplace where Avalon or one of their employees verifies this, I can finish adding them.  Either hashrate per chip or hashrate for a specific product along with the number of chips in the product (which is the other number that's way too hard to find…)

At 282 (MH/s)/chip they would be η=2,909 slightly better than bifury but still behind BFL.

[eldentyrell]

Holy insteresting. Watching. Can you add AVALON  and ASICMINER?

Sure, as soon as they post their die size, process node, and hashrate per chip.

[prof7bit]

The way you describe it its not "hash meters per second", its "hash per metersecond".

In post #1: "divide by area and then multiply with length":

This is calculated by dividing the hashrate (in H/s) by the die area in square meters and then multiplying by the cube of the process's feature size in meters

(H/s / m^2) * m

= H/(s*m)

NOT Hm/s


Edit: Sorry, i missed the cube. You are right.
its (H/s / m^2) * m^3

[mueslo]

(H*m^-12/s)

I think you mean 10^-12*H*m/s

[bulltrap]

That information was available since last year.

Quite possible!  I can't keep up with the tangled mess of threads this forum has become…  Case in point, I cannot find Avalon's statement on the hashrate per chip.  If you can post a link to that I'll add them.

I found a bunch of random third-party sites tossing around the figure of 282 (MH/s)/chip.  If somebody can post a link to someplace where Avalon or one of their employees verifies this, I can finish adding them.  Either hashrate per chip or hashrate for a specific product along with the number of chips in the product (which is the other number that's way too hard to find…)

At 282 (MH/s)/chip they would be η=2,909 slightly better than bifury but still behind BFL.

I think BFL numbers should be counted with 4GH/s per chip: https://products.butterflylabs.com/homepage-subproducts/65nm-asic-bitcoin-mining-chip.html

[2112]

That's weird, I wonder if he edited his post, the very next one is a post by me complaining that he posted the packaged size instead of the die size (in Oct 2012).

The original post date is 2012-10-24, with last edit on 2012-12-22. The code block with the process data is quoted exactly on 2012-12-13.

Quite possible!  I can't keep up with the tangled mess of threads this forum has become…  Case in point, I cannot find Avalon's statement on the hashrate per chip.  If you can post a link to that I'll add them.

I gave you already the link to the thread with posted photos of the hashing module.

Avalon advertised 3-module 66Ghash/s and 4-module 88Ghash/s device. The picture clearly shows that each module has 80 QFN chips. What else is missing?

I'm somewhat experienced with human factors in the technology education and businesses. Anytime I see PhD-level personnel unable or unwilling to do GED-level arithmetic problem there's always an interesting human story behind that situation. I can't stop wondering what is the story here.

Or maybe it is just my sense of humour failing?

[eldentyrell]

I think BFL numbers should be counted with 4GH/s per chip: https://products.butterflylabs.com/homepage-subproducts/65nm-asic-bitcoin-mining-chip.html

Thanks, you're right.  The current BFL numbers were calculated before they got their chips back, using the 7.5GH/s/chip they were quoting at the time.  I have updated their numbers.  Thanks!

Edit: this puts bitfury back on top by a hair.  I think it's really interesting how close the numbers for the three different first-gen custom chips are (BFL, bitfury, and Avalon) despite a wide range of fabrication processes -- especially compared to the huge difference between them and the FPGAs/GPUs.  I think that partially validates the hash-meters/sec metric.

[eldentyrell]

I gave you already the link to the thread with posted photos of the hashing module.

Avalon advertised 3-module 66Ghash/s and 4-module 88Ghash/s device. The picture clearly shows that each module has 80 QFN chips. What else is missing?

What's missing is enough of my free time to dig through a 42-page thread.

Anytime I see PhD-level personnel unable or unwilling to do GED-level arithmetic problem

Calm down dude.

[eldentyrell]

Edit: Sorry, i missed the cube. You are right.
its (H/s / m^2) * m^3

No worries, man.  I've made a ton of these mistakes too…

[eldentyrell]

(H*m^-12/s)

I think you mean 10^-12*H*m/s

You're quite right.  Thanks for pointing this out.

[2112]

What's missing is enough of my free time to dig through a 42-page thread.

Fair enough. But I gave you a link to a two page thread where all the relevant information was in the first half of the first page.

Calm down dude.

I'm calm, just confused, like many others here. I see you writing posts then almost immediately deleting them, it only adds to the confusion.

Anyway, here's the available Block Erupter a.k.a. ASICMINER information.

Update

Chip Specification
Technology Summary:
  130 nm
  1 Ploy
  6 Metal
  1 Top Metal
  Logic Process
Core Voltage: 1.2 V
I/O Voltage: 3.3 V
Core Frequency: 335 MHz
Core Frequency Range: 255-378 MHz
PLL Multiplier: 28
Power Consumption: 4.2 J/GHash
Number of Pads: 40
  22 Data
  18 Power
Package Type: QFN40
Packaged Chip Size: 6 mm x 6 mm

Our chips
Generation 1: Block Eruptor. 130nm with 6-8J/GH. Each chip's rated frequency is 336MHz at 1.05V. It translates to 336MH/s because it does one hash per cycle. The chips work stable and well at 392MH/s at 1.15V. Further overclocking needs proper handling of heat and power supply.

There are still no definite information about the die size. There are two posts that predate the tape-out.

Hashrate: 1.25GH/s per chip
Area: 17.5mm^2 per chip
Power Consumption: 13.3W

Hashrate: 1.00GH/s per chip
Area: 21.7mm^2 per chip
Power Consumption: 8.23W

I'm also positive that friedcat made other posts that he subsequently deleted, at least one in direct response to my post. It must have been commercially sensitive at that time.

[eldentyrell]

I see you writing posts then almost immediately deleting them, it only adds to the confusion.

I'm also positive that friedcat made other posts that he subsequently deleted

You seem to get needlessly upset/confused/emotional about the fact that people can revise their posts.

I don't see anything wrong with it, although I would favor a 60-minute limit (can't edit posts more than 60 minutes old).  If I had to painstakingly triple-check everything I wrote here before it became engraved in stone this would feel a lot more like work, and I probably wouldn't be inclined to post here.

I have my email client set to sequester outbound messages for 60 minutes, so I guess I've become accustomed to being able to do this.

Anyway, here's the available Block Erupter a.k.a. ASICMINER information.

There are still no definite information about the die size. There are two posts that predate the tape-out.

Area: 17.5mm^2 per chip

Area: 21.7mm^2 per chip

Hrm, well, in the face of conflicting information I think we're going to just have to wait.  Please let me know if anybody from ASICMINER authoritatively clarifies the situation.

Also, last I heard they were not planning on selling any chips or any products including their chips, which would mean there will never be independent verification.  Maybe the situation has changed; I don't follow the business end of this stuff too closely.  Anyways, if that's still the case I'd be uneasy about including those numbers… they could be fudged quite a bit at zero risk of getting caught.

[2112]

Anyways, if that's still the case I'd be uneasy about including those numbers… they could be fudged quite a bit at zero risk of getting caught.

I fully understand that you don't want to consider the pre-tape-out numbers for the inclusion in your table. But out of three columns there only one is unknown.

But fudging isn't zero-risk for those who ship their hardware to the end-users. It is only a matter of time until one of the Block Erupters that were sold gets accidentaly damaged and the chip will get decapped.

Check out this thread: https://bitcointalk.org/index.php?topic=231400.0 and the recent post of this user: https://bitcointalk.org/index.php?action=profile;u=23585 . For now it is just a re-confirmation of the Avalon data.

[eldentyrell]

Also, last I heard they were not planning on selling any chips or any products including their chips, which would mean there will never be independent verification.  Maybe the situation has changed; I don't follow the business end of this stuff too closely.  Anyways, if that's still the case I'd be uneasy about including those numbers… they could be fudged quite a bit at zero risk of getting caught.

I fully understand that you don't want to consider the pre-tape-out numbers for the inclusion in your table.

What I don't want to include is numbers that will never be independently verified, ever.

But fudging isn't zero-risk for those who ship their hardware to the end-users.

Yes, that's the idea.

I thought ASICMINER's plan was to never sell any chips to any third parties and sell stock instead.  Has this changed?

Check out this thread: https://bitcointalk.org/index.php?topic=231400.0

Oh, neat.  I wasn't expecting anybody to actually have a proper die photo setup.  Way cool.

[Syke]

I found a bunch of random third-party sites tossing around the figure of 282 (MH/s)/chip.  If somebody can post a link to someplace where Avalon or one of their employees verifies this, I can finish adding them.  Either hashrate per chip or hashrate for a specific product along with the number of chips in the product (which is the other number that's way too hard to find…)

At 282 (MH/s)/chip they would be η=2,909 slightly better than bifury but still behind BFL.

The stock Avalon firmware comes with settings for 282 and 300. Third-party firmwares are overclocking to 350 and above.

[RHA]

Not to add to the table yet, until the chip is working. The calculated value however explains much.

KnC Promised Figures

Design	MH/s	Device	Process node, $\lambda$	Area	η    (H*pm/s)
KnCMiner	100.0GH/s	Custom	28nm, 14nm	3025mm2	90.71

The area is package area, actual chip area will be significantly smaller, so the η value will be higher.
Edit: The die area is exact (55 mm x 55 mm), the package is 90 mm x 90 mm. Source: https://www.youtube.com/watch?v=by-je8XRCdY

Second edit: I must had misunderstood the video when I had been watching it for first time. There they stated quite clearly, the chip (the package) would be the size shown, about 60 mm x 60  mm,
not the die, which will be much smaller.
The conclusion:  η  should be significantly greater than 90.

[Anenome5]

(21-Jun) Oh my, this is terribly embarrassing.  When calculating the η-factor for bitfury last night I used the gate length instead of the feature size.  I have corrected this; please see above.  No wonder his numbers came out so high.

Any additional checking of my arithmetic would be welcome.

I was seriously wondering how his numbers were possible!

Okay, now do KNC's numbers!