Process-invariant hardware metric: hash-meters per second (η-factor)

[eldentyrell]

Data for many old and new CPUs, author colected most data we need here (die size, process node, benchmarks).

I agree.  That would show another large gap (CPU-GPU) in addition to the GPU-to-FPGA and FPGA-to-VLSI gaps.  Illuminating these sorts of generational gaps is one of the goals of the eta-factor.

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[eldentyrell]

EldenTyrell, on the website Bitfurystrikesback.com Mr. Bitfury claims a hash rate of 2.7 GH/s per chip. In this thread, you claim 2.0 GH/s per chip. Please explain and/or correct this discrepancy.

That website didn't exist the last time I updated the table.  If you click the "2GH/s" link you'll get the most recent posting by him at the time I added him to the table; it shows 2GH/s at nominal vdd and 2.26 when overvolted.  2GH/s is also the figure he gave me via private email.

I will be happy to update the entry if he confirms 2.7GH/s/chip; please just send me the link.  I'm a bit leery of switching to information from his distributors (who probably don't even have the chips yet!)

FWIW I'm still a bit mystified by the photos on his vendors' site showing a QFN chip with "5 GH/s" silkscreened onto it.

[eldentyrell]

I've been thinking a bit about a process-invariant metric of power efficiency.  This is harder because it's so easy to game the power efficiency by playing with the supply voltage -- as it decreases you get a quadratic improvement in joules/op, so in theory the measurement ought to be (ops/(sec*joules²)), but even that isn't going to be constant across all operating voltages -- there are a lot of second order effects.

On top of all this, some designs have vastly larger ranges of operating voltage than others.  Some chips only work across a narrow band of voltages, others will keep working right up to the point you fry them (my last 90nm chip did this) and all the way down to the point where the chip is consuming less than half the overall system power.

So I'm starting to think that any sort of sensible measure of power efficiency is going to have to be a graph.  A good first try might be a plot of eta-factor versus joules/op across all voltages in 25C ambient temperature.

[k9quaint]

Od the package, there is also a die rectangle shown - 43 x 43mm, quad core (multi-chip package). Then each die is 21 x 21mm.

I doubt that is the die size on the package diagram. For comparison, the Tahiti version of the AMD GPUs which was one of the largest ever chips ever had 4.31 billion transistors. Tahiti was only 398mm2 in size. If you are saying the package has 4 x 441 mm2 dies on it, then it would have a heat density higher than a nuclear reactor.

I doubt such a thing could be engineered, but if it was, it would have a hash rate far in excess of KNC's claims.

[Anenome5]

I've been thinking a bit about a process-invariant metric of power efficiency.  This is harder because it's so easy to game the power efficiency by playing with the supply voltage -- as it decreases you get a quadratic improvement in joules/op, so in theory the measurement ought to be (ops/(sec*joules²)), but even that isn't going to be constant across all operating voltages -- there are a lot of second order effects.

Why not graph it along a set range and then use the area of that graph as the metric.

On top of all this, some designs have vastly larger ranges of operating voltage than others.  Some chips only work across a narrow band of voltages, others will keep working right up to the point you fry them (my last 90nm chip did this) and all the way down to the point where the chip is consuming less than half the overall system power.

So I'm starting to think that any sort of sensible measure of power efficiency is going to have to be a graph.  A good first try might be a plot of eta-factor versus joules/op across all voltages in 25C ambient temperature.

Hmm, yeah.

[RHA]

Not to add to the table yet, until the chip is working.

Thanks RHA, I appreciate you collecting this data and putting it in table form.  Please let me know when the vendor confirms these numbers (hopefully in something other than a video…) and gives a ship date so we have know when we can reasonably expect third-party verification.

You didn't read the thread carefully enough, did you?
Just four posts earlier:

We've got info on KNC's die size and the like, how about an update to the OP?

The link links to KnC's own news with fresh technical details and especially 43 mm x 43 mm die size.
So:

KnC Promised Figures

Design	MH/s	Device	Process node, $\lambda$	Area	η    (H*pm/s)
KnCMiner	100.0GH/s	Custom	28nm, 14nm	1849mm2	148.40

[Syke]

We've got info on KNC's die size and the like, how about an update to the OP?

The link links to KnC's own news with fresh technical details and especially 43 mm x 43 mm die size.

I just can't believe the die will turn out to be that large. Nobody builds 43x43mm dies.

[k9quaint]

We've got info on KNC's die size and the like, how about an update to the OP?

The link links to KnC's own news with fresh technical details and especially 43 mm x 43 mm die size.

I just can't believe the die will turn out to be that large. Nobody builds 43x43mm dies.

I have made this point several times, but it seems to just fall on deaf ears. Plus, the schematic that people are pointing at and saying "die size" is the package schematic not the die schematic. The package is usually several times larger than the die.

For instance:


The outer dimension is the package size, the inner brownish square is the die size.

[RHA]

It seems the current formula attaches too much importance to the process node (the path width). I think it should be counted with power of 2 not 3.

No, it shouldn't… please re-read the original posting.  The feature size is counted to a power of 3 to account for reduction in area (factor of two) and the decrease in gate delay due to decreased channel length (an additional factor of one).  Please provide some sort of justification (...)

I think accounting for decrease in gate delay kind of duplicates accounting for reduction in area.
We can prepare any metric and keep to it, but a metric is useful if it gives us results conforming to real world values.
The η-factor definition implies that simply going from 130 nm to 65 nm we get 8-fold speed increase (keeping die size constant). Is it real?
My impression is the η' (using power of 2) better represents what we get. However, we have too little samples yet, to be able to decide which one actually is better.

[RHA]

We've got info on KNC's die size and the like, how about an update to the OP?

The link links to KnC's own news with fresh technical details and especially 43 mm x 43 mm die size.

I just can't believe the die will turn out to be that large. Nobody builds 43x43mm dies.

You didn't follow the link, did you?
That's a quad solution: four dies on one chip. Each one is 21.5 x 21.5 mm and should have 25 GH/s, but it gives us the same η value as one 43 x 43 mm die outputting 100 GH/s..

[Ytterbium]

I don't really think this is actually process invariant if the limiting factor is thermal, rather then purely a signal propagation delay. I mean, Avalon chips ship at 300Mhz, but are known to run at 450 and theoretically even more if it were only a transistor transition time.

You didn't follow the link, did you?
That's a quad solution: four dies on one chip. Each one is 21.5 x 21.5 mm and should have 25 GH/s, but it gives us the same η value as one 43 x 43 mm die outputting 100 GH/s..

Actually the link shows one die with four 'quads'.  For all we know, each quad is independently wired to the package, and the other three will work if one is flawed.  However, the diagram clearly shows all four units on the same die.  There is literally a single grey box with the label 'die' inside the package and containing the four 'quads'

Also 43x43 is only the size of the 'bump' on the package, it isn't necessarily the actual size of the die at all.  It could be much smaller.

[Syke]

That's a quad solution: four dies on one chip. Each one is 21.5 x 21.5 mm and should have 25 GH/s, but it gives us the same η value as one 43 x 43 mm die outputting 100 GH/s..

All the multi-die packages I've seen leave a few mm of space between dies. So the actual die size is likely to be under 20x20

[k9quaint]

We've got info on KNC's die size and the like, how about an update to the OP?

The link links to KnC's own news with fresh technical details and especially 43 mm x 43 mm die size.

I just can't believe the die will turn out to be that large. Nobody builds 43x43mm dies.

You didn't follow the link, did you?
That's a quad solution: four dies on one chip. Each one is 21.5 x 21.5 mm and should have 25 GH/s, but it gives us the same η value as one 43 x 43 mm die outputting 100 GH/s..

Everyone has followed the link. You are measuring the package area not the die area. There are no measurements associated with the ASIC section of that series of pictures. It is bizarre accounting to use the package size for one chip but the die sizes for all the others.

[eldentyrell]

We've got info on KNC's die size and the like, how about an update to the OP?

I don't see a die size on that webpage.  Please refer to the table critera in the first post -- "Die size either in an unambiguous claim by the manufacturer or die photo from a third party".  I'm not going to go about guessing the die size based on the package.

[eldentyrell]

I don't really think this is actually process invariant if the limiting factor is thermal, rather then purely a signal propagation delay.

Thermals are a power issue.  I've been pretty clear and up-front about the fact that this metric does not account for power consumption in any way.

I mean, Avalon chips ship at 300Mhz, but are known to run at 450 and theoretically even more if it were only a transistor transition time.

I don't list theoretical results.

If Avalon are willing to stake their reputation on a public claim that their product provides 450mh/s with heroic cooling, and a third party verifies that using a few randomly chosen chips, I'll list them at 450mh/s.

[eldentyrell]

Why not graph it along a set range and then use the area of that graph as the metric.

I think there's important information in the curve that isn't captured in any sort of scalar summary of it.

For example, somebody who's renting space in Douglas County cares more about the eta-factor at very power-inefficient points on the curve, while people mining at home as a hobby (are there any left?) in, say, California, care more about the eta-factor at the very power-efficient point on the curve.

Others (like me) care about the steepness and width of the curve since it's a form of insurance against future difficulty increases, which are impossible to estimate to the sort of accuracy needed for major investments.  Burn more power today to get the equipment paid off as quickly as possible, burn less power later on to keep running for as long as possible.  I'll probably be undervolting my Spartan-6 mine (which I'm amazed is still profitable) soon in order to squeeze out an extra month or two before it becomes unable to pay for its own electricity.

[Syke]

If Avalon are willing to stake their reputation on a public claim that their product provides 450mh/s with heroic cooling, and a third party verifies that using a few randomly chosen chips, I'll list them at 450mh/s.

The firmware they ship has a setting for 300 mh/s, so it's safe to include that speed in the chart.

Most miners are using a custom firmware that autoclocks. 350 mh/s is typically about where the autotuning settles for Avalon-supplied boards. I would consider that overclocking, and not appropriate to include in the chart.

To get the chips to go to 450, custom boards need to be used.

And i have some numbers to go with those from yesterday:
Slightly different air cooling setup therefore different temperatures with air cooling. (fan placement)
TL;DL : 450Mhz [9Ghash/s] - STABLE
But at the cost of 94Watts of power.

Air:
431 - 54, 48, 1.30V, 87W, stable
450 - 56, 48, 1.30V, 90W, HW Errors
450 - 57, 52, 1.34V, 94W, slightly increased error rate compared to what i normally call "stable" but close enough

Water:
450 - 54, 32, 1.34V, 94W, slightly less hw errors then with air

[Ytterbium]

I mean, Avalon chips ship at 300Mhz, but are known to run at 450 and theoretically even more if it were only a transistor transition time.

I don't list theoretical results.

If Avalon are willing to stake their reputation on a public claim that their product provides 450mh/s with heroic cooling, and a third party verifies that using a few randomly chosen chips, I'll list them at 450mh/s.

I said 450Mhz, not 450MHash/s, but that would would be about 439MHash, maybe.

Here's a quote from Bitsyncom referencing the 450Mhz figure:

was wondering how long it'd take people to notice ( and more importantly share the constant that we've released on github.)

the number you are all aiming for is 450 of course, that's not really possible on just air cooling.

The 300Mhz the unit shipped with was based on the PSU and cooling, not the chip.

[eldentyrell]

If Avalon are willing to stake their reputation on a public claim that their product provides 450mh/s

Here's a quote from Bitsyncom referencing the 450Mhz figure:

the number you are all aiming for is 450

I wouldn't call "the number you are all aiming for" staking their reputation... or even a claim.  Vague comment is vague.

Let me put it another way: is it their stated policy to replace any customer chips which won't go above 300mhz as part of the warranty?  If I bought 1,000 chips from them and tried to return the ones that wouldn't go above 300mhz would they take them back promptly for a full refund?  Has someone tried this?  These are the sorts of things to look for.  There will always be significant chip-to-chip variation; since you can't test their unsorted wafers yourself you have to rely on their public statements and returns policy (i.e. staking of reputation) to figure out what counts as "typical".

[HashFast]

Maybe it's just me, but when you tell me Bitfury has a 2800 score and KNC a score of 90, that really seems odd. Especially considering KNC's gigahash/watt is better than Bitfury's or BFL's. It really makes me question the relevance of this metric to me. Are you saying KNC, or someone, if they had access to KNC's design could replace it with a design that's 30 times more efficient? Are we saying KNC's design is basically one giant fuckup? Doesn't seem to make sense or accord with known facts.

I'm gonna assume that we simply just don't have enough technical details to make a determination and that's why KNC still hasn't been added to the OP list.

I disagree. Bitfury's power consumption is actually better than KNC's current published specs.
This η factor calculation doesn't take power consumption into consideration. It is simply a measure of the efficiency of the silicon design itself. (still very valuable IMHO)

John
HashFast