The performance claims and prices are unrealistic

[pcm81]

This saga of ASICs is really troubling from an outsider perspective. I have no orders with anyone, waiting for them to start reaching miners before I decide if I want to start a mining farm.

There is Avalon who claims to have shipped yet has no tracking numbers. How is that even possible these days? All the carriers I use give you tracking info if you ask for it or not. Two weeks is also a bit too long for stuff to get out of China unless customs is holding it for an extra long time. Feels like they haven't actually shipped more than a couple units and are stalling for time, if they show no one any tracking info then they can use that as an excuse.

Then there is BFL who keeps pushing their dates back further and further with odd or cryptic issues. Some of their excuses don't make a lot of sense when you look at the other stuff they say which makes it seem like they are further behind than they are letting on.

And then there are the rest which seem to have all folded up.

It's very disconcerting but in the end I am so glad I waited to see how things turn out.

Lets do some basic math:
For existing FPGA design the best can be had is 23MHps/J. There is no reason to anticipate an improvement in FPGA power efficiency, yes, there can be marginal reduction of overhead and the FPGA can be scaled up, but it's efficiency will not increase all that much. Based on existing designs we can anticipate 25MH/J for FPGA. There is nothing special abut ASIC, most ASIC vendors just use a custom programmed FPGA; this is called FPGA to ASIC conversion. So at best ASIC will be 50MHps/J; and i am being VERY generous here. Also, designing a product based on FPGA is one thing, designing an FPGA is completely different. It would take millions of dollars to design a new FPGA.
For the boasted hash rates of 1+GHps we are still talking 25-50 W. This is not unreasonable, until you realize that USB cable provides 5V at 0.5A, which is 2.5W. So those FPGA/ASIC designs better show a mollex connector or something... With single USB you will not hash faster than 2.25/25=0.09GH.

Now lets do some more math:
I work as an electrical engineer and salaries range from $50K/y to $180K/y depending on experience and seniority. To get an FPGA/ASIC project of this scale done you will need 2 very good engineers forking full time for a year. So we talking $200K in salary minimum. You are probably talking closer to $300K in salary by the time you add in customer support, web dev etc. The manufacturers advertise "Limited supply" to not scare miners away. From hardware alone i dont think it is at all possible to make jalapenio for $160, but lets approach this issue from the other end. If they make 10,000 units, the company needs to get $30/unit just to cover bare minimum salaries. Which means all the hardware of something like Jalapeno must cost no more than $119. For this much the best FPGA they can get is like Cyclone III, which does not look cool enough to be beefy enough to do a GH/s. At 315MHz and at least 100 clock cycles per hash (by the time you sync all ins and outs you will waste more, i am being generous here)  we are talking at 3.15 MHps per input path.  Due to the number of available gates just under 200,000 i doubt you can do more than 10 (200,000/256/100=7. hashes in parallel. I am assuming 256 routes per hash since they are 256-bit hashes and 100 gates per hash. So with 3.15MHps*10 we have 31MHps.  In Ideal perfect case, for an FPGA like Cyclone III we are talking (200,00/147,000=1.34) more HPS than from $200 spartan-6. With 100MHps on Spartan6 we would at best get 134MHps on something like Cyclone III, this 134MHps is a theoretical and unattainable number.

Conclusion: All of the FPGA promises are bs for the low prices listed. It is simply not possible to buy enough logic gates for this money to get the advertised MHps.
It would take millions of dollars to design a custom fpga and existing fpgas cost more than any of the advertised prices.

[1715261043]

1715261043

[gmaxwell]

[I split this off the Avalon thread— because it's really nothing to do with Avalon specifically.]

Conclusion: All of the FPGA promises are bs for the low prices listed. It is simply not possible to buy enough logic gates for this money to get the advertised MHps. It would take millions of dollars to design a custom fpga and existing fpgas cost more than any of the advertised prices.

None of the 'asic' vendors are claiming that their next generation products will be FPGA based— all of them have previously shipped FPGA products.  What they're claiming to do is produce custom fixed function mining chips on older processes (65nm for BFL, 110nm for Avalon).  Avalon has even posted a fair amount of their contract information with their foundry.

A miner design is substantially simpler than a FPGA or a general purpose microprocessor, and while fabrication has a high NRE the costs are often overstated. It's possible to do a run in the $100k ballpark on e.g. 130nm, or on better process via an MPW service (although usually this involves long delays). Access to state of the art process is another matter, but for these designs the efficiency gains over FPGA even on an older process can be substantial.

As an aside, MHp_s_/J appears to be confusing power and engery units. You likely want MH/J.

[greyhawk]

I'm pretty sure all Asic "vendors" claimed to not use a fpga2asic conversion but instead a full custom design.

e:fb.

[pcm81]

It's one thing to design processor application, and it is completely different task to actually design the processor.  Something like radeon 6970 gpu has 2.6 billion transistors. For FPGAs like startan-6 we are still talking billions of transistors. For someone starting from scratch, can you imagine how long it would take to draw wiring schematic with a billion components? This is what you would have to do to design a brand spanking new custom ASIC. ASIC is Application Specific Integrated Circuit, so either you have to piece it together via FPGA conversion or you have to design this circuit from scratch. This task would be not easier than it was to design FPGA like SPARTAN-6 in the first place. We talking major dollars here.

[greyhawk]

No. You buy existing IP cores from another designer (there's loads out there on offer for SHA-256) then simply pipe and kludge them together.

[DeathAndTaxes]

For existing FPGA design the best can be had is 23MHps/J. There is no reason to anticipate an improvement in FPGA power efficiency, yes, there can be marginal reduction of overhead and the FPGA can be scaled up, but it's efficiency will not increase all that much. Based on existing designs we can anticipate 25MH/J for FPGA. There is nothing special abut ASIC, most ASIC vendors just use a custom programmed FPGA; this is called FPGA to ASIC conversion. So at best ASIC will be 50MHps/J; and i am being VERY generous here.

2x energy improvement going from FPGA to ASIC?  Really please provide a link to this claim.  I have no idea (nor care) if any of the current specs are legit but FPGA are horribly energy inefficient compared to a dedicated circuit.  An energy improvement of 1000% isn't even that amazing in the move from FPGA to ASICs and 5000%+ is certainly possible.

Here is an SHA-3 academic circuit (unoptimized performing stream hashing) where the purpose wasn't even to test SHA-256 and built using archaic 130nm process.

http://rijndael.ece.vt.edu/sha3/publications/DATE2012SHA3.pdf

~150 MH/J.  Remember this is (from Bitcoin point of view) an unoptimized design as it is designed to hash an abritrary amount of data.  It is roughly 300% of what your claimed "theoretical max" would be and that is at 130nm.  At 90nm (4 generations old) it would be ~300 MH/J.  At 65nm closer to 600 MH/J.  So where did this magical 50MH/J max come from?  Just admit it ... nowhere.  It doesn't even make sense.  The whole point of the move to ASIC is to get MASSIVE reduction in energy consumption.

It's one thing to design processor application, and it is completely different task to actually design the processor.  Something like radeon 6970 gpu has 2.6 billion transistors. For FPGAs like startan-6 we are still talking billions of transistors. For someone starting from scratch, can you imagine how long it would take to draw wiring schematic with a billion components? This is what you would have to do to design a brand spanking new custom ASIC. ASIC is Application Specific Integrated Circuit, so either you have to piece it together via FPGA conversion or you have to design this circuit from scratch. This task would be not easier than it was to design FPGA like SPARTAN-6 in the first place.

Nobody designs ASICs by hand just like they don't design FPGA by hand.  They use high level libraries and design tools.  Nobody cares where each individual transistor goes just like a programmer doesn't care which exact memory address every single bit of memory goes.  It is abstracted away.  Comparing these chips to either FPGA or GPU is a false comparison.  These are SHA-256 hashes and will be significantly simpler (and smaller) than any general purpose device like a GPU or FPGA.

We talking major dollars here.

Ok.  Now say you had major dollars.  Costing major dollars =/= impossible.

[pcm81]

No. You buy existing IP cores from another designer (there's loads out there on offer for SHA-256) then simply pipe and kludge them together.

Correct, but there are 2 problems with this:
1. SHA-256 capable devices require export license, and no export to China is permitted. So you cant use china as the manufacturing site unless you just build FPGAs and then "convert" them to SHA-256 hashing devices in US.
2. The power density will not decrease as dramatically as you think. The complexity of the process will not be less, so the amount of work "gate flipping" that ASIC would need to do will be the same as it is for FPGA, the difference is that the "unused" parts of FPGA will not be sucking up power in ASIC design. I doubt that there is 90% of FPGA being currently powered on and unused in existing FPGA designs, this is what it would have to be to get 10x increase in MHPS/W in ASIC vs FPGA. The SHA single still has the power connector. It offers 10.4MH/J but for ASIC we are talking at 1000MH/J so this would mean that 99% of FPGA in the SHA single is powered on but not used for hashing... I doubt that is the case.

[Zeeks]

Correct, but there are 2 problems with this:
1. SHA-256 capable devices require export license, and no export to China is permitted.

I have heard stuff like this a few times now. Is that true? Would that be why Avalon's stuff is just "disappearing", it's actually illegal for it to enter or leave China?

[pcm81]

Correct, but there are 2 problems with this:
1. SHA-256 capable devices require export license, and no export to China is permitted.

I have heard stuff like this a few times now. Is that true? Would that be why Avalon's stuff is just "disappearing", it's actually illegal for it to enter or leave China?

Here is an example:
http://www.cast-inc.com/ip-cores/encryption/sha-256/index.html

[gmaxwell]

It's one thing to design processor application, and it is completely different task to actually design the processor.  Something like radeon 6970 gpu has 2.6 billion transistors. For FPGAs like startan-6 we are still talking billions of transistors. For someone starting from scratch, can you imagine how long it would take to draw wiring schematic with a billion components? This is what you would have to do to design a brand spanking new custom ASIC. ASIC is Application Specific Integrated Circuit, so either you have to piece it together via FPGA conversion or you have to design this circuit from scratch. This task would be not easier than it was to design FPGA like SPARTAN-6 in the first place. We talking major dollars here.

I actually did a standard cell design for a miner last year myself, starting from RTL generated off one of the open source HDL designs.  God knows if it would have actually run at an acceptable clock rate— given that I don't really know what I'm doing... but it wasn't that much work to get _something_.  A miner is insanely repetitive. The hash function is very simple. Thank god for design automation.

1. SHA-256 capable devices require export license, and no export to China is permitted.

This is nonsense. In particular, ITAR regulations very specifically exclude authentication. I am now beginning to wonder if you aren't being purposefully dishonest instead of just confused.

so the amount of work "gate flipping" that ASIC would need to do will be the same as it is for FPGA

Not so— Go look at what a directly wired 32-bit adder looks like compared to what actually gets implemented in an FPGA (in particular all the power lost to running the sram). FPGAs also waste a lot of power running the long wires in the generic routing mesh and waste a lot of power in additional flip-flops needed to make it time out acceptably.  All of these are avoided in a straighforward fixed design.

(I suppose I should note that the asic makers are claiming power efficiencies which are at the extreme upper envelope relative to their claimed processes of what I thought was possible from my designs, but I don't find this especially shocking as presumably they know what they're doing and I do not)

[pcm81]

It's one thing to design processor application, and it is completely different task to actually design the processor.  Something like radeon 6970 gpu has 2.6 billion transistors. For FPGAs like startan-6 we are still talking billions of transistors. For someone starting from scratch, can you imagine how long it would take to draw wiring schematic with a billion components? This is what you would have to do to design a brand spanking new custom ASIC. ASIC is Application Specific Integrated Circuit, so either you have to piece it together via FPGA conversion or you have to design this circuit from scratch. This task would be not easier than it was to design FPGA like SPARTAN-6 in the first place. We talking major dollars here.

I actually did a standard cell design for a miner last year myself, starting from RTL generated off one of the open source HDL designs.  God knows if it would have actually run at an acceptable clock rate— given that I don't really know what I'm doing... but it wasn't that much work to get _something_.  A miner is insanely repetitive. The hash function is very simple. Thank god for design automation.

1. SHA-256 capable devices require export license, and no export to China is permitted.

This is nonsense. In particular, ITAR regulations very specifically exclude authentication. I am now beginning to wonder if you aren't being purposefully dishonest instead of just confused.

so the amount of work "gate flipping" that ASIC would need to do will be the same as it is for FPGA

Not so— Go look at what a directly wired 32-bit adder looks like compared to what actually gets implemented in an FPGA (in particular all the power lost to running the sram). FPGAs also waste a lot of power running the long wires in the generic routing mesh and waste a lot of power in additional flip-flops needed to make it time out acceptably.  All of these are avoided in a straighforward fixed design.

(I suppose I should note that the asic makers are claiming power efficiencies which are at the extreme upper envelope relative to their claimed processes of what I thought was possible from my designs, but I don't find this especially shocking as presumably they know what they're doing and I do not)

1. In regards to export license, see the link i provided above. SHA-256 requires export license to China. Let's say i am in outside of US fixing a broken tank. Lets say to fix it i need a light bulb from "the tourch" flashlight which is sold in US. I call my boss in US to have him buy the flashlight, take out the bulb and mail it to me. He has to add the bulb to export license, because i am going to use it to fix a tank. SHA-256 is used to encrypt data, just as it is used to authenticate a user. Export license for SHA256 core will be required, just like the export license would be required for the light bulb in example i gave. US does not allow export of cripo technology to china. You can not legally send SHA-256 cores to be assembled into a product in the Chinese factory. You can send an FPGA to china to be added to pcb and then, when it gets to US u can burn the FPGA into ASIC.

[pcm81]

]I actually did a standard cell design for a miner last year myself, starting from RTL generated off one of the open source HDL designs.  God knows if it would have actually run at an acceptable clock rate— given that I don't really know what I'm doing... but it wasn't that much work to get _something_.  A miner is insanely repetitive. The hash function is very simple. Thank god for design automation.

Congratulations, you programmed an FPGA. This is not the same as designing a true ASIC implementation.

[greyhawk]

when it gets to US u can burn the FPGA into ASIC

 

What?

This doesn't even make any sense.

[Syke]

SHA-256 is used to encrypt data

How does that work? Show me how to decrypt a SHA256 hash back to its original contents.

[pcm81]

when it gets to US u can burn the FPGA into ASIC

  

What?

This doesn't even make any sense.

ASIC just means Application Specific Integrated Circuit. So, a burned FPGA is ASIC. A very bad one, but it is still ASIC. If you want to design a real, clean ASIC then you need to take SHA-256 cores, or design your own, and wire them up manually on a wafer / pcb etc. To do this you would need to have SHA-265 cores in existence at one or more steps in the manufacturing process inside of the country you are outsourcing the manufacturing to. This is where the Export of SHA-256 to China comes into play. If you take an FPGA like spartan and have china make PCB for it and send the whole thing back, you do not need export license. If you decide to send the config file to engineer in china to burn on your FPGA or if you send him SHA-256 cores (physical chips or design schematic) to be assembled in china, you are in violation of export.

EDIT:
By violation of export i meant you are breaking US law assuming you have no export license. It does not mean you cant send it, but you would need to have US government grant you export license (Long and tedious process).

[pcm81]

SHA-256 is used to encrypt data

How does that work? Show me how to decrypt a SHA256 hash back to its original contents.

Step 1, generate random contents
Step 2, hash it
Step 3, compare to a known hash. If matches and random contents makes sense you done, if does not match loop to step 1.

[gmaxwell]

Congratulations, you programmed an FPGA. This is not the same as designing a true ASIC implementation.

No, I actually produced fab ready images for a particular process that I had access to a cell library for, I was in fact specific about this in my post. Geesh. You're trying my patience

1. In regards to export license, see the link i provided above. SHA-256 requires export license to China.

The link you provided is incorrect— or overly generalized. I have exported products to china commercially which implemented HMAC for authentication. It does not require a license.

Step 1, generate random contents
Step 2, hash it
Step 3, compare to a known hash. If matches you done, if does not match loop to step 1.

You have omitted  step [2a] "Has the sun stopped shining yet?" ... what you are describing does not actually work in practice for the same reason that hashes are practically secure.

[jwzguy]

SHA-256 is used to encrypt data

How does that work? Show me how to decrypt a SHA256 hash back to its original contents.

Step 1, generate random contents
Step 2, hash it
Step 3, compare to a known hash. If matches and random contents makes sense you done, if does not match loop to step 1.

Hilarious!

[Phinnaeus Gage]

SHA-256 is used to encrypt data

How does that work? Show me how to decrypt a SHA256 hash back to its original contents.

Step 1, generate random contents
Step 2, hash it
Step 3, compare to a known hash. If matches and random contents makes sense you done, if does not match loop to step 1.

Hilarious!

Albeit not the most technical guy here, I find this thread informative, even believing pcm81, but I see doubters, and am getting confused. I dearly seek the truth on this issue, and hope a civil dialog continues.

[pcm81]

Congratulations, you programmed an FPGA. This is not the same as designing a true ASIC implementation.

No, I actually produced fab ready images for a particular process that I had access to a cell library for, I was in fact specific about this in my post. Geesh. You're trying my patience

1. In regards to export license, see the link i provided above. SHA-256 requires export license to China.

The link you provided is incorrect— or overly generalized. I have exported products to china commercially which implemented HMAC for authentication. It does not require a license.

Step 1, generate random contents
Step 2, hash it
Step 3, compare to a known hash. If matches you done, if does not match loop to step 1.

You have omitted  step [2a] "Has the sun stopped shining yet?" ... what you are describing does not actually work in practice for the same reason that hashes are practically secure.

Congratulations, you may have broken US law.
See item #10
csrc.nist.gov/publications/fips/fips198-1/FIPS-198-1_final.pdf

If SHA algorithm you used was not for 256 bits, it may not have required license.