New BFL update. 25 February 2013.

[crazyates]

How much do they pay you to brown nose for them?

^^^
This is what I've been trying to find out. Crazyates is such a fanatical BFL apologist and cheerleader that he *has* to be on the payroll.

I don't see why it bothers you guys so much that I don't consider them to be a scam...yet.

Probably for the same reason the above people spent months bashing bASIC and Avalon in their own threads.

Pot calling the kettle black as it were.

I've actually stopped even browsing thru most of the Avalon and bASIC threads, let alone taking the time to post in there. Why don't you try it? Just simply ignore every thread here on BTC with the letters BFL in the title. I think everyone will end up a bit happier.

[bonker]

I've actually stopped even browsing thru most of the Avalon and bASIC threads, let alone taking the time to post in there. Why don't you try it? Just simply ignore every thread here on BTC with the letters BFL in the title. I think everyone will end up a bit happier.

I find the whole ASIC thing fascinating, quite entertaining really.  It's such a crazy and stupid idea, that just *might* be true.

[ab8989]

The pads you see are the ones in the green area, which are normally not exposed on a packaged chip. Only on a naked die.

This is why I am so confused because what I see there is not a naked die. It looks nothing like a naked die. What is perhaps possible is that there is some layer of stuff on top of the naked die which contains then the pads that are visible on the picture. I understood that this extra layer is created during the bumping process but this wafer is taken aside from the bumping which has not actually started yet and as you can see from the wafer picture it does not contain any of that extra stuff but the wafer picture looks like a naked die. The dies on the wafer picture and the "die" on the wirebonding picture are totally incompatible to each other as their general look. So there is a discrepancy to the situation so that does not make sense from any angle you look at it.

And then there is the additional discrepancy on the square/rectangular issue on top of that.

I think that was first design for QFN which they said it failed because of thermal issues

Okay, I did not see anywhere that the CAD files were not their actual ASIC. With this new information I am not even sure the CAD files had anything to do with BFL ASIC. When you are posting something about your ASIC in february some days before expected delivery when the design change happened in early december why not post something about your actual ASIC but something else? If you do not, then sure then this created discrepancy is going to come back later to bite you in the ass. If this is the pattern of operation then I see little reason to believe anything.
 

I think Josh said they managed to make the impossible and somehow convert old design to a flip chip (check wikipedia).

Oh boy, there comes third discrepancy. The pad locations do NOT magically shift places. They are either at the edges or at the middle and nothing short of a complete redesign from the floorplanning through layout to place and route and onwards is going to make them move anywhere. There was either a complete redesign or the connection pads remain on the edges. No conversion does that. period.

The larger continuous areas from the CAD files are usually visible to the naked eye on the picture like the one made from the wafer. Why I could not see anything is not maybe a fourth discrepancy but more like a quarter of a discrepancy. They look like generic pictures from anywhere. Why not put something unique and identifying stuff there to show in the pictures?

I just fail to find one little thing in anything that supports in any way the assumption that any of the pictures has nothing to do with BFL and also nothing even a little thing to slightly indicate into the direction that they belong to the same design at all. Everything is pointing to the other direction that they are from 3 completely different projects.

Thats all.

[Puppet]

This is why I am so confused because what I see there is not a naked die. It looks nothing like a naked die. What is perhaps possible is that there is some layer of stuff on top of the naked die which contains then the pads that are visible on the picture. I understood that this extra layer is created during the bumping process but this wafer is taken aside from the bumping which has not actually started yet and as you can see from the wafer picture it does not contain any of that extra stuff but the wafer picture looks like a naked die. The dies on the wafer picture and the "die" on the wirebonding picture are totally incompatible to each other as their general look. So there is a discrepancy to the situation so that does not make sense from any angle you look at it.

And then there is the additional discrepancy on the square/rectangular issue on top of that.

I dont think you know what a naked die is, or what it looks like. What BFl posted does make sense however, they wirebonded the underside of the die to some test package. Everything you see in the yellow photo is normally covered by black epoxy/plastic/whatever.
In final production chips they will add solder bumps instead of those wires and package it in some substrate which is larger, and can have a (very) different form. Thats when it looks like a "chip".  The solder bumps are NOT what you see at the bottom of a chip, those are from the package, or they can be pins, or whatever. Bumping is not visible on a packaged chip, its inside the package.

This is basically what they made to test:
http://www.onsig.com/produc8.gif

This is how it will look like in production:
http://www.emeraldinsight.com/content_images/fig/2190090207005.png

None of this has nothing to do with the "extra layers". Thats at at the fab, where they halted production to allow for limited changes in case the test chip turns out bad.

[ab8989]

I dont think you know what a naked die is, or what it looks like. What BFl posted does make sense however, they wirebonded the underside of the die to some test package. Everything you see in the yellow photo is normally covered by black epoxy/plastic/whatever.
In final production chips they will add solder bumps instead of those wires and package it in some substrate which is larger, and can have a (very) different form. Thats when it looks like a "chip".

None of this has nothing to do with the "extra layers". Thats at at the fab, where they halted production to allow for limited changes in case the test chip turns out bad.

I might write the sentence that I am confused, but it is acually you that are. I sure know what naked die looks like and it is the look on the wafer picture. You are constantly talking about the package, which I am specifically not talking about in any way.

They cannot wirebond the underside of the die. That is raw silicon and the underside contains nothing interesting or useful to anybody. There is the stuff created in the fabbing of the die and that is all on the topside of the die. In which way the topside of the die is placed to the package (up or down) and what epoxy is put anywhere is irrelevant to this discussion.

Both the wafer picture and the wirebonded picture they should show the topside of the die that is the only side of the die that contains any functional elements of the ASIC. There is nothing on the other side of the die that is interesting in any way.

[Puppet]

They cannot wirebond the underside of the die. That is raw silicon and the uderside contains nothing interesting or useful to anywhere. There is the stuff created in the fabbing of the die and that is all on the topside of the die. In which way the topside of the die is placed to the package (up or down) and what epoxy is put anywhere is irrelevant to this discussion.

Both the wafer picture and the wirebonded picture they should show the topside of the die that is the only side of the die that contains any functional elements of the ASIC. There is nothing on the other side of the die that is interesting in any way.

The bottom (or top if you prefer, since they had to flip it) contains the interconnects. This is true for BGA or wirebonded chips, with that difference that wire bonded chips normally only have interconnects at the edge of the die and they are placed on  top. With BGA the chip is flipped so its at the bottom and you are not restricted to the edges.  Instead of wires, you use microscopic balls of lead on the interconnects of a BGA chip, thats the bumping before you solder it and glue it to its package substrate.

What BFL did was take a BGA chip, without the bumps and manually wire bond the interconnects to a test package. Thats the pic they disclosed. This is not impossible, but you will have a hard time connecting all the leads because the chip wasnt designed for this and you cant have the wires touch. Obviously this will have a different size and form as a packaged chip, which is why the form you can see (naked die) is quite different that  one on their PCBs, because you put packaged chips on there. Dont know how to make this any more clear...

This is basically what they made to test:
http://www.onsig.com/produc8.gif

This is how it will look like in production:
http://www.emeraldinsight.com/content_images/fig/2190090207005.png

[ab8989]

Since the up/down top/bottom issue seems to so deeply confuse you, then maybe it is better to change the terms and use the terms feature side or raw side of the die.

The feature side of the die is the only side that I am talking about. in the wafer picture the feature side is shown at top. In the wirebonded picture the feature side is the side that is on the top because the feature side is the only side that contains anything to wirebond anything to.

On the flip-chip package much later in the process the feature side is finally placed in which way up or down is totally irrelevant to this discussion.

Forget top/down. What I mean is that the feature-side of the die shown on top on the wirebonded picture does not look like normal feature-side of a die like one shown in the wafer picture and that is a problem to explain why is that.

The other side of the die that is the raw side that contains absolutely nothing but a hugely thick layer of raw silicon is not relevant to this discussion.

[Doctor Mushies]

I think the real question we aren't asking is whether or not BFL actually has any of the money still, not when and how they will deliver on their promise.

[greyhawk]

With this new information I am not even sure the CAD files had anything to do with BFL ASIC.

 

But they make beautiful flash memory, don't they? 

[Puppet]

Forget top/down. What I mean is that the feature-side of the die shown on top on the wirebonded picture does not look like normal feature-side of a die like one shown in the wafer picture and that is a problem to explain why is that.

You mean the solder mask?

[RHA]

That is correct. BFL originally said that refunds would be allowed "60 days past target", that is 60 days past Oct 31, that is after Dec 31:
https://bitcointalk.org/index.php?topic=87934.msg993703#msg993703  (the only reason I have the link is because I had saved it)

Strangely, the above post was deleted(!)

No, it wasn't deleted. The thread was splitted by gmaxwell and the post you are looking for is here https://bitcointalk.org/index.php?topic=139375.msg993703#msg993703

[RHA]

While not diced, the picture of the full wafer does show the separation of the individual dice.. They look awfully 'square' to me.. This single die looks rectangular.  Optical dillusion, perhaps?

No, Enigma, you simply didn't read what PuertoLibre had wrote:

Composite picture of Test Chips

Once again: Composite picture...
It's made of four different pictures. Do look at the picture more carefully and you will see boundaries of the subpictures. The wires "crossings" will help you.

[Phinnaeus Gage]

Looks to me like BFL's granny's been sippin' a tad too much Vick's Formula 44® prior to her shift. (click to view larger image)

Also, note that the faint wires don't lead to anything, for they're only connected at one end then fade into another dimension. I wonder if BFL is showing us their next gen quantum chip by mistake.


Oops! Somebody's got their wires crossed.

[Phinnaeus Gage]

Side by side comparison.



Why was time taken to present the photo on the left when clearly it's a compressed image of the one on the right?

[repentance]

Side by side comparison.



Why was time taken to present the photo on the left when clearly it's a compressed image of the one on the right?

When I was following the thread yesterday, it was BFL customers who were putting together the composite images and posting them, not BFL.  The results varied according to the poster's ability to use image manipulation software.

[Phinnaeus Gage]

Makes sense, repentance. Thanks, bud.

Now, which one of the guys crossed the wires?

[Superzero]

Side by side comparison.

http://i48.tinypic.com/35k7mdd.png http://farm9.staticflickr.com/8236/8517488290_dacd8ffee7_n.jpg

Why was time taken to present the photo on the left when clearly it's a compressed image of the one on the right?

Those pesky 38-pin packages, man.

[ralree]

Side by side comparison.



Why was time taken to present the photo on the left when clearly it's a compressed image of the one on the right?

Those pesky 38-pin packages, man.

It's a conspiracy!  They probably photoshopped it to make us think it wasn't a fake!  BFL IS OBVIOUSLY A SCAM!  Grassy nole!  Bilderbergers!  PRIORY OF ZION! 

ILLUMINATI!

[coinhammer]

[repentance]

Now we wait to learn how many of each unit BFL will manufacture from the first 5,000 chips.  No matter what the answer, it's going to piss off some people.