Will fund ASIC board for mining community. Need Hardware devs.

[ahtremblay]

Hello,

As the title says I would like to fund an ASIC mining board and make it available to the community. I believe this will not only strengthen the mining network against potential "ASIC institutional attacks" but will also help it scale faster and better with the increasing transactions number. I intend to funnel income from my main company, a DNA testing laboratory, to fund the ASIC board.

I would like to get volunteers who are good with hardware design to help this project out. So, if you are interested in the design of this board, please let me know.


My background: I have completed a bachelor degree in science (then 1 year out of 2 of a masters degree in electrical engineering), and started a high-tech dna testing laboratory 3 years after graduation. I am setting aside almost all of the profits generated by my company to fund an ASIC mining board. The reason I am saying this is because I want to build credibility to this project.

Please join me in this project if you want to help strenghen the bitcoin mining network and make it the strongest hashing network the world has ever seen!

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[SomeoneWeird]

What would we need todo?

[MoonShadow]

If you can get ArtForz to talk to you, then you just might be able to buy his design off of him. 

[ahtremblay]

Well, I need people to build the design and compile it to a TMSC process http://www.tsmc.com/english/default.htm. I understand gate logic, transistor and so on - since my background is in physics. But I have little experience with the software and the design on a large scale. I need help with the design. Someone to make a schematic in Cadence and compile it with the TMSC libraries, so that it is ready for lithography.

[MoonShadow]

ArtForz has done all of that, and even commissioned a small run of asics for his (not insignificant) mining cluster.  By reports, each card produces 200 Mhashs per second while only using 8 watts.  Most of this is hearsay, of course, but he was discussing ASICs back in September.

[ahtremblay]

I have read everything there is about ArtForz, so I know. But he is not exactly making the ASICs available to the community. This is the reason I am doing it.

[smell]

Cool idea.  I'd buy one if it were cheap enough... perhaps a kickstarter project would help offset your costs. If you're planning to make it open-source or public domain, there's no disadvantage I can foresee.

Also: is there some reason you chose TSMC right off the bat or was that an example?  I believe ArtForz used a structured asic approach which is significantly cheaper in smaller quantities...

[eturnerx]

Search for the term FPGA - this has already been discussed at length in there. The FPGA people already have working implementations. The big impediment to ASIC implementation is the cost not the talent on these forums.

[ahtremblay]

Cool idea.  I'd buy one if it were cheap enough... perhaps a kickstarter project would help offset your costs. If you're planning to make it open-source or public domain, there's no disadvantage I can foresee.

Also: is there some reason you chose TSMC right off the bat or was that an example?  I believe ArtForz used a structured asic approach which is significantly cheaper in smaller quantities...

TSMC is simply an example.

[ahtremblay]

Search for the term FPGA - this has already been discussed at length in there. The FPGA people already have working implementations. The big impediment to ASIC implementation is the cost not the talent on these forums.

I think there as been a misunderstanding. If not, then I apologize. But, I do not intend to simply release the design, as an "open source" file. I intend to finance the construction of a batch of ASICs chip based on a design, and sell them at cost-to-produce. So that miners can use them.

[hugolp]

Just commenting so I can follow the thread.

I would donate some bitcoins for this and would probably buy them.

[NetTecture]

Search for the term FPGA - this has already been discussed at length in there. The FPGA people already have working implementations. The big impediment to ASIC implementation is the cost not the talent on these forums.

I think there as been a misunderstanding. If not, then I apologize. But, I do not intend to simply release the design, as an "open source" file. I intend to finance the construction of a batch of ASICs chip based on a design, and sell them at cost-to-produce. So that miners can use them.

Count me in then. I am open for quite some boards.

[dingus]

Search for the term FPGA - this has already been discussed at length in there. The FPGA people already have working implementations. The big impediment to ASIC implementation is the cost not the talent on these forums.

Don't you dare say FPGA in front of ArtforZ, he will scold you into oblivion.

[Stefan Thomas]

Since nobody posted a link to this tweet yet - seems relevant: https://twitter.com/#!/MikePFrank/status/78409140699017216

Note that I have no idea how the terms VLSI and ASIC relate to each other, only that both are talking about chips. 

[darbsllim]

does anyone have a rough estimate of cost right now? I though the cost to produce makes it a lot more expensive than GPU mining...

[Freakin]

does anyone have a rough estimate of cost right now? I though the cost to produce makes it a lot more expensive than GPU mining...

The cost to develop it certainly does. 

[||bit]

Search for the term FPGA - this has already been discussed at length in there. The FPGA people already have working implementations. The big impediment to ASIC implementation is the cost not the talent on these forums.

I think there as been a misunderstanding. If not, then I apologize. But, I do not intend to simply release the design, as an "open source" file. I intend to finance the construction of a batch of ASICs chip based on a design, and sell them at cost-to-produce. So that miners can use them.

Hi ahtremblay. This is my first post in the forum. I'm new to the BC realm, but have been lurking a while.

The idea sounds great. However, do you mean a printed circuit card with the chip, or just the ASIC chip?
Have you any idea on what comparitive cost might be of the card compared to a GPU?   i.e. $/Mhash

Also, what kind of initial target hashrate might be desired? One could always throw more chips on the card to increase the rate... it would be more cost efficient than a chip per card. Or, perhaps, it can be designed so that multiple chips can be installed on one card (by the user)...somewhat like multiple GPU's can be installed on a MoBo.

[ahtremblay]

I have a rudimentary design right now. It is the circuit in gate array format that I designed. It is not a final design by any means, but it allows me to identify the key bottlenecks of the system, calculate gate propagation, maximum clock speed, etc. So what I have from this is; 8MHz clock, 1 hash per clock, and 100 pipelines. This could fit on low volume production run for 27$ / ASIC from TSMC. You then need to add the cost of shipping, putting it on a PCB board and add a controller, + design cost for the lithography. So basically, 800 Megahash/s, for 57$ or so (+ design costs spread across the production line). And that is without the optimization to the main bottleneck (a 7 input adder) that I am working on. So it is encouraging.

You can easily add 4-5 ASIC on each PCB board improve the Hash/$ ratio. So, with 5 ASIC per board, you would get 4GIGAHASH/s for 165$ (+ design cost). (the price of a 5850). Essentialy it makes gpu mining obselite.

[btc_family]

This sounds legitimately true from a few random sources speaking about ASIC and possible performance numbers comparing to graphics cards.
It will be interesting what you can manage to produce, sounds very economic. The ASIC stereotype is that it'll provide more speed just because it is chips on a board, why do you think that ASIC is going to work successfully with your plan to fit it to PCI(e) slots.

[hugolp]

I have a rudimentary design right now. It is the circuit in gate array format that I designed. It is not a final design by any means, but it allows me to identify the key bottlenecks of the system, calculate gate propagation, maximum clock speed, etc. So what I have from this is; 8MHz clock, 1 hash per clock, and 100 pipelines. This could fit on low volume production run for 27$ / ASIC from TSMC. You then need to add the cost of shipping, putting it on a PCB board and add a controller, + design cost for the lithography. So basically, 800 Megahash/s, for 57$ or so (+ design costs spread across the production line). And that is without the optimization to the main bottleneck (a 7 input adder) that I am working on. So it is encouraging.

You can easily add 4-5 ASIC on each PCB board improve the Hash/$ ratio. So, with 5 ASIC per board, you would get 4GIGAHASH/s for 165$ (+ design cost). (the price of a 5850). Essentialy it makes gpu mining obselite.

What about power consumption? Sounds amazing.