Will fund ASIC board for mining community. Need Hardware devs.

[ttul]

I think an open source hardware design is a great idea. The FPGA design work that is going on is just awesome. Provides a level playing field for anyone who wants to get in to the custom hardware game. At the end of the day, the innovation should not be in mining, but in the software and services to make Bitcoin more readily accessible and integrated with other ecommerce systems.

[phillipsjk]

zero scaling ability

USB hubs vs. PCIe splitters... just look up the prices!

Ethernet or USB (2.0 or 3.0) would be the way to go for sure (with Ethernet, you could do PoE and USB also allows electricity transport...)

As least USB 2.0 is limited to 2.5 Watts (5V, 500mA) I think USB 3.0 may have a high current mode, but am not sure.

Power over Ethernet is limited to about 15 watts (48V, 350mA).

In the FPGA thread they are talking 8 watts per chip. While less than the ~200Watts drawn by the GPU miners, it is still significant enough to kill the scalability you cite.

[qed]

The performance numbers sound reasonable. I have no idea why he only gets 8MHz, but this sounds like it can be improved. For a full pipeline you need roughly 100K flipflops plus all the logic. 100 times that would be 10M flipflops plus logic, which would be a rather big ASIC, but it's certainly possibly.

I had a co-worker try an Altera HardCopy synthesis and that one ended up with 20 pipelines running at >200MHz each, yielding >4GH/s per chip.

I don't trust these cost estimates at all though. The ASIC price estimate might be sensible for >10000 volumes, but the board, host interface and assembly cost estimated at $30 seems to be impossible. The VRM alone will cost that much.

He can't get over due to hazards . The propagation delay will be way too big to get any higher frequency.

[Rodyland]

Screw PCIe ASIC miners, what we really need (and will eventually get, if bitcoin doesn't tank) is a USB miner.  Put your wallet on the USB miner, plug it in to a computer and it starts hashing automatically. 

spend up to millions of dollars to fit one asic chip on a usb stick (and get limited hashing and zero scaling ability)  vs. build a PCIe card or array that can fit tons of chips and scale  hugely)?  

I would go with the latter.

You're not seeing the big picture (or at least a different picture to the one I see).

Imagine a world where btc is the default currency used in online transactions.  Mining difficulty is such that the idea of an individual building a dedicated miner is borderline lunacy - the btc made by mining is pretty much exactly equal to the electricity cost of doing so.

So who mines, given that mining is necessary for the integrity of the system?  The answer - everybody.  Your btc wallet is a keychain usb stick with a small btc client that mines whenever powered and internet connected.  Maybe only gets a few hundred MHash/sec (we're talking dedicated custom built hardware), but there are hundreds of millions of these things around the world.  We're talking Peta-hashes now.

And who pays for the portable btc wallet/miner hardware/development?  The pool owners, that's who.  Amazon gives you a free btc wallet with every purchase.  Google give you one free if you sign up for adwords.  Buy a new Toyota and it comes with a btc wallet (and a USB plug to stick it in your car, so you can pay for fuel with btc at the pump).  And the pool owners in general keep the proceeds of mining (we're probably talking transaction fee only by this stage).  Or maybe they give you a discount on your next purchase, or something like a frequent flyer system.

Anyway, that's one vision of a possible future with btc.  But one that I think is plausible if btc "takes off" and lives up to its potential.

[TheSeven]

The performance numbers sound reasonable. I have no idea why he only gets 8MHz, but this sounds like it can be improved. For a full pipeline you need roughly 100K flipflops plus all the logic. 100 times that would be 10M flipflops plus logic, which would be a rather big ASIC, but it's certainly possibly.

He can't get over due to hazards . The propagation delay will be way too big to get any higher frequency.

This can't be true if we manage to get >100MHz even on FPGAs. 8MHz sounds like the algorithm isn't pipelined at all, and calculates a hash in a single clock cycle, which is a waste, as latency doesn't matter here. What matters is throughput, and if you can get more than 20 times the throughput with just a couple of additional flipflops, you shouldn't bother about 128 clocks of latency.

[k]

Just posting to follow this thread

[kokjo]

seem interesting.

[Sukrim]

My issue with all of this is, that the hadware spec won't be Open Source, only the finished ("compiled") chips should be sold.

Sorry, but this approach creates a centralized entity again. If it's really so hard and expensive anyways to produce ASICs, you could open source the hardware plan anyways, as there won't be someone else to copy it who has not a few million bucks to play with.

I won't develop (or help developing) anything that in the end will only output a centralized miner chip that noone can audit (who says this design I implement doesn't use 10% of it's power to submit my private shares?) or improve. It is my believe that as much about Bitcoin as possible should be open source - this includes miners in software AND hardware!

[NetTecture]

My issue with all of this is, that the hadware spec won't be Open Source, only the finished ("compiled") chips should be sold.

Sorry, but this approach creates a centralized entity again. If it's really so hard and expensive anyways to produce ASICs, you could open source the hardware plan anyways, as there won't be someone else to copy it who has not a few million bucks to play with.

I won't develop (or help developing) anything that in the end will only output a centralized miner chip that noone can audit (who says this design I implement doesn't use 10% of it's power to submit my private shares?) or improve. It is my believe that as much about Bitcoin as possible should be open source - this includes miners in software AND hardware!

Is this a delusion here?

Chip production is not something that scales down. Want open source - sure. Pay for tapeout yourself. I think you overlook three really critical poitns here:

* One, multiple such designs can coexist.
* Second, this is economy of scale. Startup costs for production are HIGH, so you neeed tp produce a LOT to make it financially viable. Get the design and be surprised by 50.000 USD costs just to get the tape out - not having product a chip, plus the factory then calling for a minimum run. Not having enough money? Go buy chips.
* Third, the chip can not sumit anything (10% private shares - nice joke), it still has to go through an open source DRIVER. hich sort of makes sure it gets properly used.

But really, anyone asking for not selling the chips is delusional - I think not a sinbgle miner here can seriously finance a fully production run for special chips sensibly.

I, personally, would hbe happy to buy special boards that contain q lot of lower wattage processing power.

[TheSeven]

Sorry, but this approach creates a centralized entity again. If it's really so hard and expensive anyways to produce ASICs, you could open source the hardware plan anyways, as there won't be someone else to copy it who has not a few million bucks to play with.

Yeah, open source the VHDL code, or even the die layout. And you still can't verify that the chips you would buy can't have been tampered with.
The only way to verify that would be building the chips yourself - which you can't do for obvious reasons.

Do you build your own GPUs and graphics cards today? You certainly don't. And a graphics card (oh, and it has a closed source firmware/driver!) could tamper with the data more easily than a pure sha256 bruteforcing accelerator ASIC (like it's being planned here) could.
The worst that the ASIC could do is not finding some shares that would have been valid. This can easily be detected, and the only way in which the vendor could profit from that is a slightly lower difficulty.

This of course assumes that the network interface isn't on the ASIC itself (which doesn't make sense for cost reasons anyway), but instead running on some PC (for PCIe accelerator cards) or on some ARM SoC with open source firmware (for standalone mining boards).

[LegitBit]

How about Thunderbolt?

Apple's usage is limited to 10W on laptops, but since it is based on PCIE (it IS pcie)) it could deliver 75W on desktops.

http://www.intel.com/technology/io/thunderbolt/index.htm

zero scaling ability

USB hubs vs. PCIe splitters... just look up the prices!

Ethernet or USB (2.0 or 3.0) would be the way to go for sure (with Ethernet, you could do PoE and USB also allows electricity transport...)

As least USB 2.0 is limited to 2.5 Watts (5V, 500mA) I think USB 3.0 may have a high current mode, but am not sure.

Power over Ethernet is limited to about 15 watts (48V, 350mA).

In the FPGA thread they are talking 8 watts per chip. While less than the ~200Watts drawn by the GPU miners, it is still significant enough to kill the scalability you cite.

[foo]

Following.

[max3t]

I just want to say that I find this whole ASIC-Thing very interesting and a great engagement. If I'd be sure that I could get those babies running, I would throw say a thousand bucks in the ring.

As for high initial costs we could open a website which tracks the spendings from each member to the project and then calculate the board price as "sum of expenses / boards delivered".
Then at first only a small amount could be produced (for say 1500$ per unit). Later when a second (equally large) order needs to be placed in china, resulting in a price of 500$ because no more design etc has to be done, the overall price would be 1000$ bucks, which every board would cost then. then the members who payed 1500$ initially would have like 500$ cash-back or discount on further boards. they would practically a board for free.
As I stated above both orders were equally large, so you notice that this calculation makes no sense. but you get the idea, hmm?

[Modoki]

I still would think the very best Idea would be to open source the layout and design in the first place.
If you want to produce them as well, go on, people who are not able to produce their own will buy yours.
So why don't just go both ways?
Greets, M

[Modoki]

well, is it really a call for investors?
There would need to be some hardware guys with a reputation or an escrow service.
they see cash, they start to develop.
asic is done, op tells it is done. people set up a pledge if it is released, he releases it and receives the pledge.
sounds like a neat idea, doesn't it?
greets, m

[ahtremblay]

Casper,

Where have I asked for money? I asked for help developing the software by contributing free time to the project. Granted, 1 forum member has privately expressed interest to invest and I have started talks with this person. I said, I will finance this project. If anything, I should be the one worried about getting scammed. I received a bunch of emails from people will little to no experience or knowledge offering help for a fee. If anything, I should be worried that their design won't work, making me waste my money.

If I say that I will finance the design of an ASIC board and release the design for free. As well as order a batch based on the design and also release that affordable. Of course people will say its a good idea... since there is no disadvantages or risk to anyone. Why would anyone say its a bad idea.

[ijuz]

I asked for help developing the software by contributing free time to the project.

The software looks like the most simple part of such a project, IMO.

[Rodyland]

I have to raise a red flag as this could be a potential investor scam. Here is something to consider when evaluating the OP's intention.

Name:    Rodyland
Posts:    19 (3.167 per day)
Date Registered:    June 06, 2011, 04:20:54 am
Posted at June 12, 2011, 09:38:41 am:
http://forum.bitcoin.org/index.php?topic=14910.msg206771#msg206771

"You're not seeing the big picture (or at least a different picture to the one I see).

Imagine a world where btc is the default currency used in online transactions...So who mines, given that mining is necessary for the integrity of the system?  The answer - everybody...Maybe only gets a few hundred MHash/sec (we're talking dedicated custom built hardware), but there are hundreds of millions of these things around the world.  We're talking Peta-hashes now."

Big number of customers...

None of the accounts have associated content such as an e-mail or website URL.

Best regards,
Casper

You are a conspiracy theorist nut.  My profile has an email, I just choose not to show it publicly.  I don't have a website of my own.  You want my TFN? (That's tax file number, closest Aussie equivalent to an SSN I believe).

Tool.

[njloof]

Casper, great, you've made your point. Now please settle down and prepare to either accept your kudos for being right or to give your apologies if you are wrong.

[TheSeven]

I think there as been a misunderstanding. If not, then I apologize. But, I do not intend to simply release the design, as an "open source" file. I intend to finance the construction of a batch of ASICs chip based on a design, and sell them at cost-to-produce. So that miners can use them.

This can very well be interpreted as "not just open source, but also affordable physical chips, as doing that on your own isn't affordable", and if this is the intention here, that's perfectly fine.

He's basically taking all the financial risk, and only asks for some help on the design/software side. The only scam I could imagine is that he builds the chips with our help and then decides to use them all for his own mining instead of selling them at affordable prices as promised.

To get back to the technical aspects:
Why do you only get 8MHz out of that circuit? How is it constructed? All the SHA256 rounds in one huge tree of combinational logic? Or is it pipelined?
Do I understand correctly that each SHA256 unit on it gets a throughput of one hash per clock? How deep is the pipeline, i.e. how many clocks is the delay between input data arrival and result availability?