Re: Stratix-5 A7 or D5 project 01.05.2013 update

[Signus]

I understand everything, but software is software and real tests are real tests.
As I said the hasrate is 1-3ghash/s, maybe little more, and the power usage is something near 60W, but I would like to put exact numbers.
With the software I don't think I could get exact numbers.

Well where are you getting the estimates? Or are you just speculating on numbers? I'd like real numbers too.

[kingcoin]

I understand everything, but software is software and real tests are real tests.
As I said the hasrate is 1-3ghash/s, maybe little more, and the power usage is something near 60W, but I would like to put exact numbers.
With the software I don't think I could get exact numbers.

Actually it's the software which will tell you your hashing performance, not the hardware.

Using your current hardware to check how fast it will run is risky as you don't know the process parameters of the particular part you have in the lab. It might be way faster than it's labeled speed grade. Your next production batch might not be.

Run the RTL code through Quartus. Then you run static timing analysis in Quartus and it will tell you the max clock frequency the slowest part will operate at. Multiply this with the number of hash operation the architecture can perform on each clock and you have your hash rate.

Or you have to make a design which will dynamically increase the clock speed until it fails to calculate nonces and then step down the clock until it starts to produce correct results. This is more complex as you have to make sure that timing errors don't propagate into your safe clock domain. It's also more complex to make sure your thermal solution can handle this behavior.

For power you should run a simulation of the full implementation of the design and generate a VCD (Value Change Dump) file which will show the toggle rate for all the nets in the design. This can be included in a power analysis tool like PowerPlay. This will give you a good estimate of the power consumption of the FPGA.

60W sounds like a lot for a single FPGA.

[funnow]

As I write on an earlier post, I get information from a person, who is working with FPGA, and I think He is not a member in this forum.
I would like to see how much power usage will figure out cyclone chips from Kncminer, so I don't think 60W is a lot.

[Signus]

I understand everything, but software is software and real tests are real tests.
As I said the hasrate is 1-3ghash/s, maybe little more, and the power usage is something near 60W, but I would like to put exact numbers.
With the software I don't think I could get exact numbers.

Actually it's the software which will tell you your hashing performance, not the hardware.

Using your current hardware to check how fast it will run is risky as you don't know the process parameters of the particular part you have in the lab. It might be way faster than it's labeled speed grade. Your next production batch might not be.

Run the RTL code through Quartus. Then you run static timing analysis in Quartus and it will tell you the max clock frequency the slowest part will operate at. Multiply this with the number of hash operation the architecture can perform on each clock and you have your hash rate.

Or you have to make a design which will dynamically increase the clock speed until it fails to calculate nonces and then step down the clock until it starts to produce correct results. This is more complex as you have to make sure that timing errors don't propagate into your safe clock domain. It's also more complex to make sure your thermal solution can handle this behavior.

For power you should run a simulation of the full implementation of the design and generate a VCD (Value Change Dump) file which will show the toggle rate for all the nets in the design. This can be included in a power analysis tool like PowerPlay. This will give you a good estimate of the power consumption of the FPGA.

60W sounds like a lot for a single FPGA.

Well in this case he's wanting to implement FPGA's that nobody has used for mining yet (to our knowledge) mainly because of their cost. So that's why I'm curious where he's getting these numbers, because 60W for a FPGA is a lot.

And if you're getting this info from a person, either have them join the forums or give you information that you can quote. I don't like empty numbers without some amount of backing.

[kingcoin]

As I write on an earlier post, I get information from a person, who is working with FPGA, and I think He is not a member in this forum.

Then you should forward my message above to this person.

I would like to see how much power usage will figure out cyclone chips from Kncminer, so I don't think 60W is a lot.

60W is a lot for a single FPGA , especially if it's a Cyclone. But it's not a lot for a miner full of Cyclone chips.

[funnow]

As I write on an earlier post, I get information from a person, who is working with FPGA, and I think He is not a member in this forum.

Then you should forward my message above to this person.

I would like to see how much power usage will figure out cyclone chips from Kncminer, so I don't think 60W is a lot.

60W is a lot for a single FPGA , especially if it's a Cyclone. But it's not a lot for a miner full of Cyclone chips.

I'm not talking about Cyclone, but Stratix V

[kingcoin]

As I write on an earlier post, I get information from a person, who is working with FPGA, and I think He is not a member in this forum.

Then you should forward my message above to this person.

I would like to see how much power usage will figure out cyclone chips from Kncminer, so I don't think 60W is a lot.

60W is a lot for a single FPGA , especially if it's a Cyclone. But it's not a lot for a miner full of Cyclone chips.

I'm not talking about Cyclone, but Stratix V

That's what I thought too, but I got a little confused parsing your sentence regarding the Cyclones. But as I said initially 60W is a lot for a single FPGA.

[funnow]

As I write on an earlier post, I get information from a person, who is working with FPGA, and I think He is not a member in this forum.

Then you should forward my message above to this person.

I would like to see how much power usage will figure out cyclone chips from Kncminer, so I don't think 60W is a lot.

60W is a lot for a single FPGA , especially if it's a Cyclone. But it's not a lot for a miner full of Cyclone chips.

I'm not talking about Cyclone, but Stratix V

That's what I thought too, but I got a little confused parsing your sentence regarding the Cyclones. But as I said initially 60W is a lot for a single FPGA.

No, no never mentioned Cyclones so stay tunned on this post.

[funnow]

I have contacted other 2 companies for more information about their chips.
I have some helpers here from the forum for the design and testing part -> so something is moving here also

[kingcoin]

As I write on an earlier post, I get information from a person, who is working with FPGA, and I think He is not a member in this forum.

Then you should forward my message above to this person.

I would like to see how much power usage will figure out cyclone chips from Kncminer, so I don't think 60W is a lot.

60W is a lot for a single FPGA , especially if it's a Cyclone. But it's not a lot for a miner full of Cyclone chips.

I'm not talking about Cyclone, but Stratix V

That's what I thought too, but I got a little confused parsing your sentence regarding the Cyclones. But as I said initially 60W is a lot for a single FPGA.

No, no never mentioned Cyclones so stay tunned on this post.

You did mention Cyclones in post #83. It's even quoted in your message. But as I said I could not understand that sentence, e.g. if you refer to Cyclones in your own project or in some other project.  Anyways, good luck on your project.

[funnow]

As I write on an earlier post, I get information from a person, who is working with FPGA, and I think He is not a member in this forum.

Then you should forward my message above to this person.

I would like to see how much power usage will figure out cyclone chips from Kncminer, so I don't think 60W is a lot.

60W is a lot for a single FPGA , especially if it's a Cyclone. But it's not a lot for a miner full of Cyclone chips.

I'm not talking about Cyclone, but Stratix V

That's what I thought too, but I got a little confused parsing your sentence regarding the Cyclones. But as I said initially 60W is a lot for a single FPGA.

No, no never mentioned Cyclones so stay tunned on this post.

You did mention Cyclones in post #83. It's even quoted in your message. But as I said I could not understand that sentence, e.g. if you refer to Cyclones in your own project or in some other project.  Anyways, good luck on your project.

I have only mentioned, but not for my project. Thanks for a good luck, I think I need it.

[funnow]

Mods please close this topic, I will open another one because I decided to start the project with a fresh ASIC chip.
New topic will be open as soon as I have a team ready. Probably all EU located.
Thanks again for help and my best wishes for all!

[erk]

Mods please close this topic, I will open another one because I decided to start the project with a fresh ASIC chip.
New topic will be open as soon as I have a team ready. Probably all EU located.
Thanks again for help and my best wishes for all!

Kewl

[dan99]

Mods please close this topic, I will open another one because I decided to start the project with a fresh ASIC chip.
New topic will be open as soon as I have a team ready. Probably all EU located.
Thanks again for help and my best wishes for all!

Kewl

Start project with fresh asic chip? how long would it take 2 produce the chip? 2014?