Are current generation ASICs SHA256(SHA256(x)) implementations?

[mustyoshi]

Does anybody know if they are explicitly double SHA256, or if they simply run the SHA256 twice.
This is important because it also denotes their usefulness outside of Bitcoin.

[tom_o]

Potentially the fastest password cracking the world has ever seen...

[crazyates]

https://en.bitcoin.it/wiki/Protocol_specification

[mustyoshi]

https://en.bitcoin.it/wiki/Protocol_specification

That doesn't tell me if the ASIC hardware does SHA256(SHA256(x)) or if it is SHA256(x) twice.

[stevegee58]

https://en.bitcoin.it/wiki/Protocol_specification

That doesn't tell me if the ASIC hardware does SHA256(SHA256(x)) or if it is SHA256(x) twice.

Yes it does.  You must have missed the part where it said  "dhash(a) = sha256(sha256(a))"

[mustyoshi]

https://en.bitcoin.it/wiki/Protocol_specification

That doesn't tell me if the ASIC hardware does SHA256(SHA256(x)) or if it is SHA256(x) twice.

Yes it does.  You must have missed the part where it said  "dhash(a) = sha256(sha256(a))"

Okay let me rephrase my question, is it possible for the ASIC hardware to just do SHA256(x) instead of SHA256(SHA256(x))?

[stevegee58]

https://en.bitcoin.it/wiki/Protocol_specification

That doesn't tell me if the ASIC hardware does SHA256(SHA256(x)) or if it is SHA256(x) twice.

Yes it does.  You must have missed the part where it said  "dhash(a) = sha256(sha256(a))"

Okay let me rephrase my question, is it possible for the ASIC hardware to just do SHA256(x) instead of SHA256(SHA256(x))?

No.  The ASIC miner can only do the one thing and that's all.  That's whey they're called "Application Specific Integrated Circuits"

[mgio]

Try looking at the specs that Avalon has been releasing?

[turtle83]

https://en.bitcoin.it/wiki/Protocol_specification

That doesn't tell me if the ASIC hardware does SHA256(SHA256(x)) or if it is SHA256(x) twice.

Yes it does.  You must have missed the part where it said  "dhash(a) = sha256(sha256(a))"

Okay let me rephrase my question, is it possible for the ASIC hardware to just do SHA256(x) instead of SHA256(SHA256(x))?

AFAIK neither. You cant use the ASIC to compute SHA256(x) OR SHA256(SHA256(x)) . A lot of the logic is inside the chip. Basically it gets the data similar to bitcoin protocol, and runs a loop to find the right nonce. The chip itself wont return the generated hashes. Also, the accepted size of "x" would probably be only the exact size used in bitcoin protocol. So I think your quest to find alt purpose is in vain.

[tom_o]

https://en.bitcoin.it/wiki/Protocol_specification

That doesn't tell me if the ASIC hardware does SHA256(SHA256(x)) or if it is SHA256(x) twice.

Yes it does.  You must have missed the part where it said  "dhash(a) = sha256(sha256(a))"

Okay let me rephrase my question, is it possible for the ASIC hardware to just do SHA256(x) instead of SHA256(SHA256(x))?

AFAIK neither. You cant use the ASIC to compute SHA256(x) OR SHA256(SHA256(x)) . A lot of the logic is inside the chip. Basically it gets the data similar to bitcoin protocol, and runs a loop to find the right nonce. The chip itself wont return the generated hashes. Also, the accepted size of "x" would probably be only the exact size used in bitcoin protocol. So I think your quest to find alt purpose is in vain.

That's good IMO, I had a bad feeling about 5Ghash+ password crackers being released into the wild with no oversight.

[stevegee58]

That's good IMO, I had a bad feeling about 5Ghash+ password crackers being released into the wild with no oversight.

Oversight?  You're sounding like a statist.

I say release 5 Gh/s password crackers into the wild and let the chips fall where they may!

[turtle83]

That's good IMO, I had a bad feeling about 5Ghash+ password crackers being released into the wild with no oversight.

Oversight?  You're sounding like a statist.

I say release 5 Gh/s password crackers into the wild and let the chips fall where they may!

+1

Id expect this to be the what people replacing FPGA with ASIC do...  Time to use scrypt with a very high N for security purposes...

[Schrankwand]

https://en.bitcoin.it/wiki/Protocol_specification

That doesn't tell me if the ASIC hardware does SHA256(SHA256(x)) or if it is SHA256(x) twice.

Yes it does.  You must have missed the part where it said  "dhash(a) = sha256(sha256(a))"

Okay let me rephrase my question, is it possible for the ASIC hardware to just do SHA256(x) instead of SHA256(SHA256(x))?

AFAIK neither. You cant use the ASIC to compute SHA256(x) OR SHA256(SHA256(x)) . A lot of the logic is inside the chip. Basically it gets the data similar to bitcoin protocol, and runs a loop to find the right nonce. The chip itself wont return the generated hashes. Also, the accepted size of "x" would probably be only the exact size used in bitcoin protocol. So I think your quest to find alt purpose is in vain.

That's good IMO, I had a bad feeling about 5Ghash+ password crackers being released into the wild with no oversight.

Well, that could at least force people to migrate to AES or possibly Threefish soon with whatever they do.

[k9quaint]

That's good IMO, I had a bad feeling about 5Ghash+ password crackers being released into the wild with no oversight.

Oversight?  You're sounding like a statist.

I say release 5 Gh/s password crackers into the wild and let the chips fall where they may!

+1

Id expect this to be the what people replacing FPGA with ASIC do...  Time to use scrypt with a very high N for security purposes...

Or SHA-512. But yeah, bitcoin FPGAs usually take getwork/stratum data as input and give as output a 32-bit nonce. They do not transmit the hashes outside the chip because 300Million x 256bit per second is 76.8Gbits of bandwidth. So no, they can't really be used to crack passwords.
I would imagine that ASICs use the same sort of paradigm.

[turtle83]

That's good IMO, I had a bad feeling about 5Ghash+ password crackers being released into the wild with no oversight.

Oversight?  You're sounding like a statist.

I say release 5 Gh/s password crackers into the wild and let the chips fall where they may!

+1

Id expect this to be the what people replacing FPGA with ASIC do...  Time to use scrypt with a very high N for security purposes...

Or SHA-512. But yeah, bitcoin FPGAs usually take getwork/stratum data as input and give as output a 32-bit nonce. They do not transmit the hashes outside the chip because 300Million x 256bit per second is 76.8Gbits of bandwidth. So no, they can't really be used to crack passwords.
I would imagine that ASICs use the same sort of paradigm.

Yeah ASIC work in similar manner IMHO, but what i mean is FPGA can be re-programmed to find hashes. No need for bandwidth. Send target hash. let fpga run bruteforce , and return valid cleartext if found. 200MH sha256(sha256(x)) ~ 400 MH sha256(x).

6 character lower case + upper case + number = 56800235584 combinations or ~56800 MH so 142 seconds on single lx150
prolly take lesser time since data sizes is small... dunno...

[k9quaint]

That's good IMO, I had a bad feeling about 5Ghash+ password crackers being released into the wild with no oversight.

Oversight?  You're sounding like a statist.

I say release 5 Gh/s password crackers into the wild and let the chips fall where they may!

+1

Id expect this to be the what people replacing FPGA with ASIC do...  Time to use scrypt with a very high N for security purposes...

Or SHA-512. But yeah, bitcoin FPGAs usually take getwork/stratum data as input and give as output a 32-bit nonce. They do not transmit the hashes outside the chip because 300Million x 256bit per second is 76.8Gbits of bandwidth. So no, they can't really be used to crack passwords.
I would imagine that ASICs use the same sort of paradigm.

Yeah ASIC work in similar manner IMHO, but what i mean is FPGA can be re-programmed to find hashes. No need for bandwidth. Send target hash. let fpga run bruteforce , and return valid cleartext if found. 200MH sha256(sha256(x)) ~ 400 MH sha256(x).

6 character lower case + upper case + number = 56800235584 combinations or ~56800 MH so 142 seconds on single lx150
prolly take lesser time since data sizes is small... dunno...

Yep. Fortunately FPGAs are pricey and make up a very small portion of the hashrate. The current generation of ASICs cannot be easily re-purposed to crack passwords. As you say though, one could design an ASIC to crack password hashes pretty easily.