Actually 2-chips in 1 package *has* been done ref
SFARAD from early 2015. Was supposed to mine
X11 scrypt and BTC.
The company failed miserably and now their datasheet has been stolen/plagiarized by scammers and is being used to peddle Wonder-of-the-Ages Vapor Miners.
SFards was a merger between GridSeed (which made the original "dual miner" chip, Scypt and SHA256 with their GC3355) and WiiBox (which I believe made some of the controllers for the "bigger" Gridseed miners).
The only reason the GC3355 survived for a significant period of time is that it was quite efficient on the Scrypt side - it's SHA256 side got passed VERY quickly - and that Scrypt wasn't attracting nearly as much competition in ASIC chips as SHA256 was.
For perspective - the GC3355 was PROFITABLE by the time Litecoin hit $8 (and possibly a bit before that) in the current surge, and if you had 3c/KWH electric it was close to break-even even during the long Litecoin run in the $4-$5 range - because it's competition was NOT all that much more efficient. Even the L3+ is only about 10 times as efficient, despite being a few "nodes" newer tech and at least 2 full generations of miner newer.
They failed because their chip was MARGINAL on SHA256 efficiency even when they announced it, took forever to get the miner to market, and the miner turned out to be VERY badly designed at the board level (an issue the Gridseed miners ALSO had) and unreliable, and the SHA256 efficiency BY THE TIME THEY BROUGHT IT TO MARKET was inferior to the competiton, but the price was so high the machine could NOT compete on the Scrypt side (despite being marginally more efficient than most existing Scrypt miners).
The problem with doing a "dual algo" chip like that is you have to split the chip between the two - you CAN'T resuse much of it if you are doing multiple algos (exception for X11/X13/X15 which incorporate multiple different algos in series, so you CAN resuse most of the chip even if you're running one of the "lesser" algos like X11).
FPGA isn't efficient enough to compete with ASIC where ASIC exists - FPGA is about flexability.