What is use of this forum since people that are registered not able to make posts on desired topics nor to send messages to other members?
Is not easiest to make private this forum than to accepts new members that have no any right?
Is there other OPEN forum that is related to BitCoin FPGA development?
This will sound rude but it's not intended to.
Ok, but...
Those rules are there to actually keep people like you out.
And what do you know about me to tell that?
I know that sounds harsh but quite often, newbies haven't spent the time to read up on how this community works and then they make life annoying for people who have been here for a long time.
Well... I don't want to waste my life spending "long time" on this forum to be able to make post to appropriate thread on this forum.
From your post, it's clear you've not spent a moment to read the newbies post. It would take you 3 minutes and it would explain why those rules are there.
Yep I already told that it is idiotic rule. Why ANYONE can register to this forum WITHOUT conformation from email that is included on registration?
The very content of your post suggests that if you were given free access to the forums you'd post a question that's been asked a million times or you'd post in the wrong sub-forum (because you've not taken the time to see which forum you should post in). As it is, the questions you've asked have been asked several times a day and yet you still need to ask it...
I have no time to play so you can repost this questions to "Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013)"
It is already send to "fpgaminer" but it is not answered.
Hello,
Since I'm not able to make posts on this forum. I'm using this way...
I have some questions to you and other members...
I did't know about BitCoin until last month.
I have some experience with FPGA so I have looked on some sources just for fun.
I'm not familiar with verilog much, but .... Is it sha256_pipes2.v correct pipeline design?
Design and timings are strange.
Anyway in free time I'm working on pipelined design that use 2 input adders that gives results for spartan 6 350mhz(350Mh/s (one hash per clock)) using 71000 ff/LUT, same design gives 550mhz(550Mh/s)on Kintex...
And questions are:
If I want to use 2 or more cores on one FPGA, can it be NONCE devided into groups or not?
Like first core nonce start from 0 to 7fffffff and second from 80000000 to ffffffff? because there is posibility
that sometime there exist 2 or more correct nonces for one work. Or every core have to ask for different job and for every work nonce MUST start from 0 to ffffffff?
Is there any real documentation of protocol?
Also is there anybody who have destroyed spartan6 tried to cut top of chip to look on supstrat if it have wires bounded to top or bottom of supstrat. If it is bounded on bottom side then top of chip can be removed to get better thermal connection to heatsink.
Also how is calculated h/s. Is it number of executed hashes per sec or it is calculated using number of founded nonces per time?
B.R
