KNCMiner and their 'magic' SHA256 alogorithm

[k9quaint]

I am really not interested in Open Days, just plain old transparency. It works.

Got one on order, have you?

Date Registered:    June 02, 2013, 10:19:42 PM  OK!

Yep, pretty transparent attack on KNC. Notice how he has not addressed any rebuttals to his statements.

[Vanderi]

No, this is'nt Josh, just a concerned citizen. In all fairness to him and BFL, they've never put out any technical misinformation about their products. 

hoooboooy that's Josh right there

[shapemaker]

No, this is'nt Josh, just a concerned citizen. I doubt that Josh has the time or inclination to worry about what KNC may or may not claim at present. In all fairness to him and BFL, they've never put out any technical misinformation about their products.

Err... here's a partial list of lies/omissions/misinformations about BFL products:

• chip power estimates
• chip production details
• estimated hashing power
• PCB specs
• all kinds of part delivery dates
• product specification changes
• production capacity
• shipping schedule

While not everything on that list is strictly technical, it does illustrate how anything that comes out of BFL "PR" machine should be viewed with suspicion. Anyone care to add more?

[thomashrev89]

I am really not interested in Open Days, just plain old transparency. It works.

Got one on order, have you?

Open days is all about transparency.... Yes i got an order, KNCminer has been cool from day 1.

i dont know, but i think troll..

[bitfury]

Well. That 36% speedup is likely "old" trick of balancing delay between EFGH and ABCD pipelines... I consider this as an old trick that everybody knows now :-) So nothing new and unusual.... I think today this is public domain and well-understood technique at least of those who deal with miners :-) Avalon has it for example.

Very important feature. There exists several ways to balance depending on performance of underlying cells, but idea is the same. BFL by the way seems not to implement it in their FPGA products that I suspected about 1.5 years ago when tried to benchmark my code with quartus estimations. There can be actually some invariant transformations of pipeline that however produce different timing balance. Best of course when you get equal delays.

Look carefully code below, it is what I actually use in last design. You should see extra subtraction for example. It may seem like unnecessary operation, but it helps to balance delays and get overall better performance. Trick like that existed already in my earliest bitstreams in end of 2011 So now there's more tricks but they are not related with logic models, but layout issues.

To sum up - if they claim they use such balancing - means that they worked really well and aware of details, unlike BFL did, good sign. I think they could disclose now more :-)))

Code:

  always @(posedge clk) begin
    /* Compute round expander values */
    w0 <= w1; w1 <= w2; w2 <= w3; w3 <= w4; w4 <= w5; w5 <= w6; w6 <= w7; w7 <= w8; w8 <= w9; w9 <= w10; w10 <= w11; w11 <= w12; w12 <= w13; w13 <= w14; w14 <= w15;
    if (s[0]) w15 <= `REV(win); else w15 <= w0 + `S0(w1) + w9 + `S1(w14);

    /* Compute HGFE */
    hr <= gr; gr <= fr; fr <= er;
    if (s[2]) er <= `REV(el); else er <= `E1(er) + `CH(er, fr, gr) + agwk;

    /* Compute ABCD */
    dr <= cr; cr <= br; br <= ar;
    if (s[4]) ar <= `REV(al); else ar <= `E0(ar) + `MAJ(ar, br, cr) + ds;

    /* PREPARE */
    kr <= `REV(k);
    ds <= er - cr;
    agwk <= w15 + ar + gr + kr;
  end

[Loredo]

"An ASIC Design for a High Speed Implementation of the Hash Function SHA256 (384, 512)", Dadda, Machetti, Owen (2004)

I don't know what the precise language is which you're taking to task.  But if KNC or OrSoC's guys found, studied, and implemented this or another implementation scheme for SHA256, then it's semantics you're arguing.

What I mean is this:  there is only one exact square root that maps uniquely on a real number.  But if it mattered, and you had a way to make a value converge to full float accuracy faster than mine, could I take you to task if you said you had a better square root algorithm than I did, if we both got the same correct value?

And, no, I don't have a KNC box on order.  I don't have any hardware on order.  The mining ship has sailed for anybody that doesn't have their own unlimited supply of chips and the facility to build the boards.

[Rampion]

So to any of you that are prepared to swallow the shite that KNC put out: Beware.

I'm not saying they are scammers, but they are dishonest with their information, to put it mildly.

While you may be right in saying this is the "magic" behind KnC:s algo, the way you express your thoughts reminds me of another forum dweller here...

Is that you, Josh?

What magic? What algo?

There's no KnC ASIC yet. It's just a promise. All this is just mental masturbation.

[brontosaurus]

Glad to see some of you have actually started to think. I have actually designed asics before, and am well aware of what is real and what is not in device specifications and performance. I would advise anyone with an interest in the asic implementation of SHA256 to read some of the academic prior art available as I have done. Then let's hear your thoughts.

I have no alligience to any of the asic companies, but I hate misuse of data and bad 'technospeak'. I also think any company that wants your money should answer your questions without you having to ask them. If you think differently, then you're an idiot.

As for BFL, they dug themselves into a hole and did'nt try to get out. They need a good PR man to repair their tattered reputation,and to do something to restore the faith in their customers.

Problem is here, you all want to be rich - nothing wrong in that - but don't make the mistake of financing your future competition.

[bitfury]

Good that you designed asics. Well in prior publications (prior to 2011) I haven't seen that such balancing was well covered. There's really MANY solutions like that, basically I have explored likely most if not all of them. These have different implications depending on underlying cell implementation... But - is it really something that would be published ? For me it seemed like good r&d job that anyone who would like to produce optimized algorithm should pass. And it was surprising that many developers actually ignored such optimizations. I remember that I got to them much much earlier than say I understood underlying low-level structure of spartan fpga. So not looks like something impossible complex. Especially for those who pretend to be experts.

[innovation]

I am not an expert and can not pretend to be. But I think there are revolution ways to break the balance of ACIS design.
Maybe the details of KNCminer ACIS design is not convenient to disclose. 
So No news is good news.
Just waiting three months to see the result.
So many thanks to your deeply explanation of different ACIS design.

[Trongersoll]

perhaps, when they say they are "improving the Algorithm" they are refering to their implimentation of it. Perhaps their implimentation had issues and they improved them.

[DPoS]

Dadda has an adder type named after him - and designed a method of reducing delay paths on an actual asic.

so where is Dadda's miner if he so supa??

[dan99]

Dadda has an adder type named after him - and designed a method of reducing delay paths on an actual asic.

so where is Dadda's miner if he so supa??

Ya where is your supper miner, seems like you know everything about Asics ...

[brontosaurus]

Believe me, if I had access to 400k$ I would get one built. But I don't and so have work for a living like everyone else.

I know of at least two groups that are actually doing this on 20nm technology at the moment, and they aren't planning on selling their product to the masses. Frightening thought.

As for Mr. Dadda, I suspect that because of his abilities and reputation he's paid extremely well and has other interests. Read some of his papers, you'll find it a worthwhile exercise, he's a very clever man.

[idee2013]

Knew I'd find this eventually:

"An ASIC Design for a High Speed Implementation of the Hash Function SHA256 (384, 512)", Dadda, Machetti, Owen (2004)

These guys came up with a re-timing pipeline which increases Maximum Clock Speed on a regular SHA engine by 36%. No new algorithm - you cannot 'improve' the existing one, this is simply an exercise to reduce critical path delay on an ASIC (not an FPGA)

So to any of you that are prepared to swallow the shite that KNC put out: Beware.

I'm not saying they are scammers, but they are dishonest with their information, to put it mildly.

Read into that what you will.

it's finickiness. The wording seems this way, thereby  everybody is able to understand it without detailed knowledge .

[KS]

Well, even if they do make a product (ASIC+what goes around), KNCMINER are still full of shit and your dealings with them should be carefully evaluated.

That said, if they ship and don't scam everyone, they'll just be like any other lame business you have to deal with in this "line of work".

@Brontosaurus: forget getting ANY financial info from them. They just magically used their 5000 EUR in company equity to get the project off the ground (oh, BTW that and the preorder money... - they hadn't even selected the foundry yet, they were to do it around Wednesday if the report is correct). But they don't call it equity, the seem to think it's some Gov tax (at least that's what they want you to believe, justifying the fact they didn't put, say, 20x more in it...)

[brontosaurus]

KS, it goes back to the basic questions I put in my earlier post. You have to select a foundry early on to get access to their technology design rules and cell libraries, unless you already have said or are using COT. KNC clearly don't have the first and are'nt using the second. So they are still at least 6 - 8 weeks away from tape out, and another 12 weeks to prototypes. That's end November by my estimation, so forget getting any product this year.

Can you see why I'm concerned about what companies say / promise? One lie leads to another and so on....

[CanaryInTheMine]

The real question to ask yourself is:
What do I think an improvement of x% to the SHA256 algorithm means?

Increase in difficulty

[KS]

KS, it goes back to the basic questions I put in my earlier post. You have to select a foundry early on to get access to their technology design rules and cell libraries, unless you already have said or are using COT. KNC clearly don't have the first and are'nt using the second. So they are still at least 6 - 8 weeks away from tape out, and another 12 weeks to prototypes. That's end November by my estimation, so forget getting any product this year.

Can you see why I'm concerned about what companies say / promise? One lie leads to another and so on....

I know exactly what you mean. However, I can't say what ORSoC is capable of but I'm starting to think they are also full of it. They were still working on the FPGA while claiming the ASIC was ready, but then the fab isn't selected yet.

They said the fab or ASIC maker (so I assume the fab) will complete the ASIC design (so take the FPGA bitstream and convert it to an ASIC?), since they are not doing it themselves. So there is a possibility for slippage right there (trusting 3rd parties to keep your schedule - yeah right), then tape out in x weeks (say 10, to keep a tight schedule). No prototype, no testing, just production. If they are lucky, that'd put tape out sometime in September, then there is packaging, assembly, shipping, etc. It's "doable", but until their pipeline is not tested...

[Rampion]

What puzzles me is the fact that Bitfury already has its chips, and they plan to ship in September as KnC.

KnC has no chips whatsoever, in fact they plan to receive them in August and send them directly to production. It seems that they want to do in one month or less what takes other players at least 2/3 months.

I have to admit that the fact that Bitfury's chips are already in the wild being tested as I'm writing makes me kinda uncomfortable as a KnC customer. We are entering very fast in very competitive times, in which every week is crucial and determines if ROI will be achieved or not.