Hi Freeworm,
I don’t know if you are from btc-garden. I am quite interested in this opensource idea, I fully support a opensourced mining asic.
However, I think the best way to make it work is to do it for free.
Personally I think 200 bitcoins for an FPGA code is too expensive, since you can easily get it from openFPGAminer project where it is free and opensourced. What’s your improvement?
That doesn’t mean I don’t what to contribute on this.
As I am also a chip designer myself, I am more interested in the technical level details. There are several question marks in my mind.
1. As I know, it is a long way to go from FPGA verification to an asic chip. Unless you don’t care about the performance. FPGA has its own architecture, and optimized for flexibility.
2. According to my experience, to get 300MHps is not easy. As you don’t have the final physical design ready yet, how did you estimate a performance of 300MHps in the 110nm technology? Only using FPGA tools like Quatus is not possible at all. Which EDA tools did you use to estimate the performance?
3. The SHA256 core is complex and contains tens of thousands of logic cells. For one or two designers, manually routing the design would be as hard as going the moon by foot. Typically the layout is done with EDA tools automatically. You mentioned 20-30days of work for the layout, and does this mean fully manual layout, or using EDA tools for the routing? I heard that Intel designed their early CPUs fully manual and I believe it since they have many personal months. But BFL claimed their chip “100% Hand routed for performance density” and I doubt about it. I totally agree if it is only for the packaging
4. There are many technique details for an efficient asic SHA256 core. E.g. In a FPGA implementation the PLL is only used for generating the clock. But in an asic the clock can be used with multiphase, which can’t be simulated in FPGA.
5. You mentioned the most difficult part is prototyping in FPGA, but I think the most difficult part is to optimize the design. That includes optimization of the algorithm, the layout of the chip etc. It seems you haven’t provided any technical details about it now. Getting 100MHps in FPGA is not difficult at all. If you provide slack information in your asic design that would convince more people.
I guess the initial purpose of the project is to profit, now making it opensource means no profit. But asking for 200BTC is still charging something. What is your vision behind this?
Anyway I fully support the opensource idea, and I hope more and more discussions going on with this topic. I am glad to get involved into making an opensourced asic miner.
