Gridseed GC3355 -Hybrid Scrypt/SHA256 ASIC

[greaterninja]

1 GENERAL DESCRIPTION
GC3355 is high performance and low power SHA256 processor designed by GRIDCHIP. With
advanced technology and highly integrated design, GC3355 target to provide multiple function and low
cost solution in SHA256 application fields.
 
Key feature:
 160 BTC Units
 4 LTC Units
 BTC mode up to 2.25G/s BTC Hash Rate, with 2.4W/GHash
 LTC mode up to 60K/s LTC Hash Rate
 Due-Coin mode up to 1.75G/s BTC Hash Rate + 60K/s LTC Hash Rate, or up to 2.25G/s BTC Hash
Rate + 38K LTC Hash Rate
 Highly integrated with PLL and Pre-Calculation Engine
 Support dual configuration and report interface, UART and Custom-Defined 2-Wires Bus
 Support Crystal and Oscillator
 Fully adjustable clock frequency

http://gridseed.com
https://github.com/gridseed/gc3355-doc
https://github.com/gridseed/cpuminer

It is possible to do scrypt with a fpga, so that implies asic is possible too.  I have seen a POC.  With that said I am extremely skeptical if it can hit above 60k/s rate.  Let alone even 10k/s scrypt hashing rate.

[jayeeyee]

You lost me at LTC.  When you say 60K/s.. does that equate the same to 60KH/s?

[Sy]

Power efficiency is nice but the number doesn't change that much, you need 10 chips (600$?) to outmatch a 280x (300$?), yes power is the key but this is not "a game changer" just a shift in power consumption, the kh numbers are pretty much the same.

[ar88]

Power efficiency is nice but the number doesn't change that much, you need 10 chips (600$?) to outmatch a 280x (300$?), yes power is the key but this is not "a game changer" just a shift in power consumption, the kh numbers are pretty much the same.

Du(al)-Coin mode up to 1.75G/s BTC Hash Rate + 60K/s LTC Hash Rate, or up to 2.25G/s BTC Hash
Rate + 38K LTC Hash Rate

comes with 1.75GH/s of BTC hash rate as well..when running 60Kh/S LTC, doubt one 280x can do that?

[Sy]

Power efficiency is nice but the number doesn't change that much, you need 10 chips (600$?) to outmatch a 280x (300$?), yes power is the key but this is not "a game changer" just a shift in power consumption, the kh numbers are pretty much the same.

Du(al)-Coin mode up to 1.75G/s BTC Hash Rate + 60K/s LTC Hash Rate, or up to 2.25G/s BTC Hash
Rate + 38K LTC Hash Rate

comes with 1.75GH/s of BTC hash rate as well..when running 60Kh/S LTC, doubt one 280x can do that?

Yep that's a neat feature, doesn't concern the ltc network at all though, ppl react like this will really hit the ltc network hard but in fact, it doesn't change much at all, availability will suck as usual - you need 1,058,750 chips to just double the current diff and bring it up to 4200...

Don't get me wrong, i'll most likely buy some of these since it's really really nice to have but it won't change things as much as most here tend to think.

[Sy]

Yeah but i bet they don't even think about it, its alot of work to put 1 million chips into working devices - why even bother if you can just sell them at much higher instant profit  just sayin, that would only double the current diff, raising the ltc diff to 10k and above is not an easy task xD

[Tomatocage]

When will they be available and how can I buy one?

[Gator-hex]

Scrypt requires high speed access to memory so I'm gonna say this is bull until there is some evidence it works.  

[senseless]

It is possible to do scrypt with a fpga, so that implies asic is possible too.  I have seen a POC.  With that said I am extremely skeptical if it can hit above 60k/s rate.  Let alone even 10k/s scrypt hashing rate.

My FPGA is hashing at 60Kh/s, granted, it's a 5000$ fpga, but it is possible.

Litecoin will work fine on asic with on-die sram. You can even calculate the hash rate based on known factors.

Code:

200 / (2048 * 8) * Ncores = scrypt hashrate in Mh/s based on 200Mhz clock speed

It appears what they've done to keep the chip small is to implement 4x 256Kbit on-die memories for hashing as I haven't seen anything mentioned about an off chip memory. At 55nm 1mbit of sram is about 7.63mm2. At 28nm 1mbit of sram is 3.88mm2. The max size for QFN-48 (which is a 7x7mm package) silicon is around 4x4mm so have roughly 16mm2 of space. They couldn't have implemented 4x 1mbit as it would be to large (with an exception for the 28nm which would be 15.52mm2, but even then there wouldn't be enough room for all those bitcoin hashers). The speed and stats are certainly within the realm of possibility.

Looks like their site is up. Didn't work the first time.

55nm chip, so definitely within the realm of possibility.

[tacotime]

Scrypt requires high speed access to memory so I'm gonna say this is bull until there is some evidence it works.  

I'm sure someone will reverse engineer these sooner rather than later, and then we'll be looking at a lot of potential scrypt ASICs hitting the market.  SEMs aren't that costly these days.

[senseless]

Translated auto-reply from sales address:

Important Note: We currently do not have any place in the pre-sale, Taobao are fake, the official website information please prevail.

Follow weibo.com/gridseed That is our official microblogging.

Relating to the purchase, agents, price issues,
Please wait for our official website www.gridseed.com announced
If you need to apply the agent, please specify in the message header "application proxy" and described their own information, and other advantages, if only one sentence is difficult to our attention that, thank you.

For technical discussion, please www.cybtc.com gridchip zone discussion, where maintenance by our technical team.

Documents to download, go to the open source project: github.com/gridseed

If we are unable to respond to you request, please understand, because the volume of mail than we expected, but we will read every message.

I found more pictures on some chinese site:
http://www.cybtc.com/thread-3005-1-1.html

[Egon]

Anyone try to sign up for the Weibo feed?

[tacotime]

It appears what they've done to keep the chip small is to implement 4x 256Kbit on-die memories for hashing as I haven't seen anything mentioned about an off chip memory. At 55nm 1mbit of sram is about 7.63mm2. At 28nm 1mbit of sram is 3.88mm2. The max size for QFN-48 (which is a 7x7mm package) silicon is around 4x4mm so have roughly 16mm2 of space. They couldn't have implemented 4x 1mbit as it would be to large (with an exception for the 28nm which would be 15.52mm2, but even then there wouldn't be enough room for all those bitcoin hashers). The speed and stats are certainly within the realm of possibility.

Looks like their site is up. Didn't work the first time.

55nm chip, so definitely within the realm of possibility.

That's interesting. If they did implement the SRAM on chip, I guess the could maximally fit 14 scratchpads (14 x 128 KB).  If with 8 they could reach 84 KH/s at let's say a theoretical 0.750 W, we'd max out on a single chip at 147 KH/s and 1.3 W.  Not too shabby if these only cost about $5-10 each to produce on 55 nm QFN-48.

I'd guess they aren't using straight up scratch pads, though, but rather the TMTO desynchronization trick from Solar Designer.  Regardless, the physical limitations as above should still be the same.

[senseless]

It appears what they've done to keep the chip small is to implement 4x 256Kbit on-die memories for hashing as I haven't seen anything mentioned about an off chip memory. At 55nm 1mbit of sram is about 7.63mm2. At 28nm 1mbit of sram is 3.88mm2. The max size for QFN-48 (which is a 7x7mm package) silicon is around 4x4mm so have roughly 16mm2 of space. They couldn't have implemented 4x 1mbit as it would be to large (with an exception for the 28nm which would be 15.52mm2, but even then there wouldn't be enough room for all those bitcoin hashers). The speed and stats are certainly within the realm of possibility.

Looks like their site is up. Didn't work the first time.

55nm chip, so definitely within the realm of possibility.

That's interesting. If they did implement the SRAM on chip, I guess the could maximally fit 14 scratchpads (14 x 128 KB).  If with 8 they could reach 84 KH/s at let's say a theoretical 0.750 W, we'd max out on a single chip at 147 KH/s and 1.3 W.  Not too shabby if these only cost about $5-10 each to produce on 55 nm QFN-48.

I'd guess they aren't using straight up scratch pads, though, but rather the TMTO desynchronization trick from Solar Designer.  Regardless, the physical limitations as above should still be the same.

On second look, they are using QFN-64 not QFN-48 so they do have some extra wiggle room and may have even been able to do 4x 512Kbit scratchpads.

[fasmax]

I find it interesting the similarities between this chip and the Avalon gen2 chip.
Even the pin outs are similar

[Cheshyr]

I find it interesting the similarities between this chip and the Avalon gen2 chip.
Even the pin outs are similar

That's just them being cautious.  If we're familiar with the pinout, it's easier for us to design a board to support it.

I really want to get my hands on a chip to develop.  It's kinda painful how difficult it is to get dev samples of new chips these days.

[goxed]

It is possible to do scrypt with a fpga, so that implies asic is possible too.  I have seen a POC.  With that said I am extremely skeptical if it can hit above 60k/s rate.  Let alone even 10k/s scrypt hashing rate.

My FPGA is hashing at 60Kh/s, granted, it's a 5000$ fpga, but it is possible.

Litecoin will work fine on asic with on-die sram. You can even calculate the hash rate based on known factors.

Code:

200 / (2048 * 8) * Ncores = scrypt hashrate in Mh/s based on 200Mhz clock speed

It appears what they've done to keep the chip small is to implement 4x 256Kbit on-die memories for hashing as I haven't seen anything mentioned about an off chip memory. At 55nm 1mbit of sram is about 7.63mm2. At 28nm 1mbit of sram is 3.88mm2. The max size for QFN-48 (which is a 7x7mm package) silicon is around 4x4mm so have roughly 16mm2 of space. They couldn't have implemented 4x 1mbit as it would be to large (with an exception for the 28nm which would be 15.52mm2, but even then there wouldn't be enough room for all those bitcoin hashers). The speed and stats are certainly within the realm of possibility.

Looks like their site is up. Didn't work the first time.

55nm chip, so definitely within the realm of possibility.

Hey senseless, which code are you using for LTC? Thanks a lot

[Anotheranonlol]

Scrypt requires high speed access to memory so I'm gonna say this is bull until there is some evidence it works.  

its demonstrated already..

I find it interesting the similarities between this chip and the Avalon gen2 chip.
Even the pin outs are similar

avalon gen2 is designed by this team

Not too shabby if these only cost about $5-10 each to produce on 55 nm QFN-48.

it's not QFN-48 and cost less than 1$

[MZD]

I wonder how much these will cost and how long it will take to get them into a working machine. Any theories?

[fasmax]

Not long at all. Probably all ready hashing. Just need to refine the software would be my guess .