Purchasing a Bitforce unit = betting on stagnation?

[fred0]

I think that the next year will be interesting at least.

If we are following the Gartner Hype Cycle, and have passed the "trough of disillusionment," then a stabilized bitcoin price is in our future.

Increased bitcoin price won't force current GPU miners out, and enhanced profitability for the FPGA mining operations will be good news.

In any case, I would NOT be betting on stagnation.

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[DeepBit]

Well you can't lump together all ASIC as they get vastly higher efficiency as you move up the cost ladder.
sASIC - lowest upfront cost, highest per unit cost.  Still roughly 2x the efficiency of FPGA (in performance per watt and performance per $).
cell based ASICS.  higher upfront cost, significant risk, much lower per unit cost.

Aren't sASICs (structured ASICs) cell-based ? :)

[DeathAndTaxes]

Well you can't lump together all ASIC as they get vastly higher efficiency as you move up the cost ladder.
sASIC - lowest upfront cost, highest per unit cost.  Still roughly 2x the efficiency of FPGA (in performance per watt and performance per $).
cell based ASICS.  higher upfront cost, significant risk, much lower per unit cost.

Aren't sASICs (structured ASICs) cell-based ?

The lines kinda blur but sASIC are generally classified as a static computational layer and a custom routing layer.  The computational layer is mass produced and combined w/ custom routing layer in the fab.  It can be considered a form of cell based ASIC. Still it has the limit in that the computational layer is fixed (like a FPGA).  It has a set number of components which can't be changed.  Since the design requirements will never exactly line up w/ the capabilities of any FPGA/sASIC there is wasted die space.

However there are methods of making a completely "custom chip" (no standardized logic layer) using "cells".  The cells are pre-designed low level silicon.  Using higher level software a designer combines cells to make a "custom" chip from standardized blocks.  Design software can then build a custom mask.  You gain higher efficiencies over sASIC because you can choose exact number of cells, chip size, routing, etc.  Upfront costs go way up and per unit costs go way down.  

Of course the terms aren't exactly set in stone.  I guess in one sense of the word all structured ASICS are cell based but at least my understanding is that structured asics involve a fixed computational layer.

[DeepBit]

However there are methods of making a completely "custom chip" (no standardized logic layer) using "cells".  The cells are pre-designed low level silicon.  Using higher level software a designer combines cells to make a "custom" chip from standardized blocks.  Design software can then build a custom mask.

This is real ASIC. Of course everyone uses standard libraries of elements, many of them are produced by the fabs like IBM.
I don't think anyone still laying out routes and silicon pieces by hand :)

The difference between sASIC and ASIC is that the first one uses custom masks only for routing, that's why it's cheap.

[DeathAndTaxes]

However there are methods of making a completely "custom chip" (no standardized logic layer) using "cells".  The cells are pre-designed low level silicon.  Using higher level software a designer combines cells to make a "custom" chip from standardized blocks.  Design software can then build a custom mask.

This is real ASIC. Of course everyone uses standard libraries of elements, many of them are produced by the fabs like IBM.
I don't think anyone still laying out routes and silicon pieces by hand

The difference between sASIC and ASIC is that the first one uses custom masks only for routing, that's why it's cheap.

I never said cell based ASIC aren't "real" ASICs just that they have lower upfront cost and higher per unit cost than a full custom design.

http://en.wikipedia.org/wiki/Application-specific_integrated_circuit#Standard-cell_design

Generally the definition of cell based ASIC is where you can't design below the cell level.  This reduces design complexity but will result in less than perfect utilization of the silicon compared to a complete custom design.  A cell may be hundreds of even thousands of gates.  That simplifies routing, design, and mask creation but has overhead and wasted die space.  Cell based designs will never be as efficient (performance per watt or dollar) than a custom design but are much simpler to create resulting in significant time, resource, upfront cost savings.

Thus generally unless millions of units will be built the higher upfront cost of a full custom design will never be recovered.

[Inaba]

When comparing FPGA to potential future competitors (ASIC or really any technology) you can't compute the purchase cost of the item purchased in the past against the cost of the item just purchased and compare the W:MH or $ ratio's directly.

You need to factor in what it's paid back in the interval between when you purchased it and when the future technology is made available.

If you pay $700 for a BFL now and in 6 months you've made $350 with it, then a nifty ASIC version comes out for $500, you aren't comparing a $500 device against a $700 device, you are comparing a $350 device against a $500 device, and run your calculations from that point.  

A device generating money RIGHT NOW is worth an infinite number of devices that might generate money in the future... until you have both devices generating money RIGHT NOW, you can't really compare them directly.  When they are both available, compare them at their current costs, not at their costs in the past and future.  Lest, if you follow that logic, you can deduce that sASICs purchased in 3 years are more valuable and thus sASICs purchased in 1 year, since those in 3 years will be cheaper than those next year.  However, that sASIC available in one year, being less valuable than the one available in 3 years is a reason to wait - in three years, that one available is going to be less valuable than the one available in 5 years, so wait until then.  Repeat this cycle in 5 years.

[DeathAndTaxes]

When comparing FPGA to potential future competitors (ASIC or really any technology) you can't compute the purchase cost of the item purchased in the past against the cost of the item just purchased and compare the W:MH or $ ratio's directly.

You need to factor in what it's paid back in the interval between when you purchased it and when the future technology is made available.

Good points.  The real risk would be a more efficient system hitting the market before you have paid back a significant cost of capital.  Even if sASICS or more exotic silicon tech eventually hit the market IMHO it will be years long enough for any FPGA to have long since paid for its cost of capital.

The greatest "threat" to 45nm FPGA is a .... 28nm FPGA.  The good news is there is likely at least a year (probably two) before 28nm FPGA are available to the general public at reasonable prices and those miners gets built and start driving up difficulty.  While a 45nm FPGA will be inferior to a 28nm FPGA in 24 months it will also have 24 months of cashflow under it's belt.

[Epoch]

When comparing FPGA to potential future competitors (ASIC or really any technology) you can't compute the purchase cost of the item purchased in the past against the cost of the item just purchased and compare the W:MH or $ ratio's directly.

You need to factor in what it's paid back in the interval between when you purchased it and when the future technology is made available.

If you pay $700 for a BFL now and in 6 months you've made $350 with it, then a nifty ASIC version comes out for $500, you aren't comparing a $500 device against a $700 device, you are comparing a $350 device against a $500 device, and run your calculations from that point.  

A device generating money RIGHT NOW is worth an infinite number of devices that might generate money in the future... until you have both devices generating money RIGHT NOW, you can't really compare them directly.  When they are both available, compare them at their current costs, not at their costs in the past and future.  Lest, if you follow that logic, you can deduce that sASICs purchased in 3 years are more valuable and thus sASICs purchased in 1 year, since those in 3 years will be cheaper than those next year.  However, that sASIC available in one year, being less valuable than the one available in 3 years is a reason to wait - in three years, that one available is going to be less valuable than the one available in 5 years, so wait until then.  Repeat this cycle in 5 years.

This is a good perspective on the situation.

Unfortunately even the BFL units are still not shipping and may not be for another month. So although you can PAY for the BFL unit today, you won't be able to MINE with it yet. Still, once you can, the comparison can be made in the manner you've outlined.