The SoC is proven silicon. Including RAM, it accounts for less than 2% of the die, and improves functionality and performance.
Using the same voltage and clock rate for all areas of the chip is common in simpler ASIC designs, and could cause issues similar to those mentioned by 2112. Fortunately, our design isn't that simple, and our Lead ASIC Designer is very experienced.
Another answer from a marketroid.
Regardless of the design two most important things will be the substantially the same on the whole chip surface: temperature and electrical noise. The SoC would have to be super-overdesigned to survive both the temperature and the noise where the hasher cores still operate with tolerable fault rates. Such SoC controllers do exist (e.g. radiation hardened designs with lockstepping and other fault tolerance features) but they require additional manufacturing steps/masks. This would be a complete waste for the remaining 98% of the circuit and will increase both the NRE costs of the masks and the time to fabricate the wafers. Most likely also the software miners would have to be changed to actually take advantage of the SoC, when it isn't compatible with Linux (e.g. ARM Cortex-M instead of Cortex-A).
I do not negate the possibility of the Lead ASIC Designer being very experienced. He's probably experienced in the low-power design for the battery-operated devices and didn't have time to fully understand the coin mining market requirements, which are more akin to the high-power, mixed-signal integrated circuits. And being very familiar with hammers he simply viewed mining as another nail to hammer in: just use SoC to bang two clocks.
And the man who has two clocks never knows the correct time.
Anyway, lets see if the "Lead ASIC Designer" will post here or if this is another Novello.
