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Author Topic: Has anyone asked for a quote to create a BTC-miner?  (Read 2398 times)
Wandering Albatross
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March 13, 2012, 05:34:48 PM
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I'm new to BTC and FPGA. I see lots of discussion and lots of good-intended vaporware. I see the real thing too in ztex,icarus,x6500,bfl. (I miss any?)

But has anyone actually talked with a company that is in the business of creating FPGA designs and products?
I know there are some companies that take FPGA designs and automate the FPGA design to an ASIC product.

I may look into it just for the experience and see what happens. I'm sure some of you here already know where this will take me so chime in.

I envision getting some quotes, settling on one and then crowd funding for that.
Part of the request for the quote will require that the entire design be free (as-in freedom). Will that change the price?

Has it been tried already?

[UPDATES]
Wed Mar 21, 2012 I have sent out three requests in the past week or so. No replies yet.

BTC: 1JgPAC8RVeh7RXqzmeL8xt3fvYahRXL3fP
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Inspector 2211
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March 13, 2012, 05:52:46 PM
 #2

I'm new to BTC and FPGA. I see lots of discussion and lots of good-intended vaporware. I see the real thing too in ztex,icarus,x6500,bfl. (I miss any?)

But has anyone actually talked with a company that is in the business of creating FPGA designs and products?
I know there are some companies that take FPGA designs and automate the FPGA design to an ASIC product.

I may look into it just for the experience and see what happens. I'm sure some of you here already know where this will take me so chime in.

I envision getting some quotes, settling on one and then crowd funding for that.
Part of the request for the quote will require that the entire design be free (as-in freedom). Will that change the price?

Has it been tried already?

A full custom ASIC at current gate lengths (28 nm, 35 nm, 40 nm, 45 nm) is now several million.

I actually asked a buddy of mine who works as an ASIC designer here in Silicon Valley whether we could just slap Stefan's Verilog code into his Synopsis or Cadence workstation at work, and I'll pay the 25 grand for a multi-project wafer somewhere, and his answer was, yes, he could certainly compile the Verilog code into RTL, and maybe even simulate the RTL, but there's much more to an ASIC than that, for instance the physical layout and physical verification, which he cannot do by himself. Now, if I had two friends at that particular Silicon Valley company, one a Verilog/RTL guy and the other one a physical design guy, maybe it would be possible to "moonlight" this over the course of several months...

But I don't and it isn't.
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March 13, 2012, 06:09:24 PM
 #3

I'm new to BTC and FPGA. I see lots of discussion and lots of good-intended vaporware. I see the real thing too in ztex,icarus,x6500,bfl. (I miss any?)

But has anyone actually talked with a company that is in the business of creating FPGA designs and products?
I know there are some companies that take FPGA designs and automate the FPGA design to an ASIC product.

I may look into it just for the experience and see what happens. I'm sure some of you here already know where this will take me so chime in.

I envision getting some quotes, settling on one and then crowd funding for that.
Part of the request for the quote will require that the entire design be free (as-in freedom). Will that change the price?

Has it been tried already?

A full custom ASIC at current gate lengths (28 nm, 35 nm, 40 nm, 45 nm) is now several million.

I actually asked a buddy of mine who works as an ASIC designer here in Silicon Valley whether we could just slap Stefan's Verilog code into his Synopsis or Cadence workstation at work, and I'll pay the 25 grand for a multi-project wafer somewhere, and his answer was, yes, he could certainly compile the Verilog code into RTL, and maybe even simulate the RTL, but there's much more to an ASIC than that, for instance the physical layout and physical verification, which he cannot do by himself. Now, if I had two friends at that particular Silicon Valley company, one a Verilog/RTL guy and the other one a physical design guy, maybe it would be possible to "moonlight" this over the course of several months...

But I don't and it isn't.

Hrmf, too bad.
Wandering Albatross
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March 13, 2012, 06:22:49 PM
 #4

Quote from: Inspector 2211
A full custom ASIC at current gate lengths (28 nm, 35 nm, 40 nm, 45 nm) is now several million.

Ok so an ASIC seems to be out of the question as of now. But what about just an FPGA design?

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Inspector 2211
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March 13, 2012, 06:36:10 PM
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Quote from: Inspector 2211
A full custom ASIC at current gate lengths (28 nm, 35 nm, 40 nm, 45 nm) is now several million.

Ok so an ASIC seems to be out of the question as of now. But what about just an FPGA design?

The best hope now seems to be EldenTyrell, who has managed to fit three instances of SHA-256 (single SHA, not double SHA) into a Spartan6-150, however he wants to be compensated at market rates for his (admittedly brilliant) work, and thus it is unclear whether his bitstream will ever become publicly available.

Then there is wondermine, who certainly does not lack youthful exuberance and enthusiasm and maybe he can duplicate EldenTyrell's work and put it in the public domain.

If none of them comes through, it looks like we are stuck at 210 MH/s (Stefan == ZTEX).
Wandering Albatross
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March 13, 2012, 07:37:53 PM
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Quote from: Inspector 2211
..stuff I knew...

As the topic of this thread is about contracting out the design, I was asking what that would cost for an FPGA from a real company.
i.e. don't take it all the way to an ASIC

I am collecting a list of vendors and will see.

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March 13, 2012, 07:52:30 PM
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Quote from: Inspector 2211
..stuff I knew...

As the topic of this thread is about contracting out the design, I was asking what that would cost for an FPGA from a real company.
i.e. don't take it all the way to an ASIC

I am collecting a list of vendors and will see.
Why? They will just try to sell you a low performance, tightly-rolled design. No need to reinvent the wheel.

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March 13, 2012, 08:35:29 PM
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and I'll pay the 25 grand for a multi-project wafer somewhere,

If you could add another zero to that sum, you might want to look at doing an altera hardcopy. Its the logical next step after FPGA; significant power consumption and (given enough volume) cost advantages, without the excessive NRE of a full custom asic. Should also be much easier to develop, if you have a working FPGA implementation, and a bundle of cash, you have all you need.

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March 15, 2012, 12:37:23 PM
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How much would going from Spartan 6 to Altera Hardcopy (and then to a board that actually plugs in to a USB port) be? And whats the estimated time to have these bad boys delivered to your door step?
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March 15, 2012, 12:50:58 PM
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How much would going from Spartan 6 to Altera Hardcopy (and then to a board that actually plugs in to a USB port) be? And whats the estimated time to have these bad boys delivered to your door step?


Infinite. Smiley

Spartan = xilinx FPGA
Altera Hardcopy = Altera sASIC.

You would need a competitive FPGA using an Altera chip and not just any chip a chip that they have a HardCopy equivelent for.

Altera "Spartan equivelent" is the Cyclone and there is no path to HardCopy from a Cyclone.  You would need a Stratix family chip (and they start @ $4K ea).
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March 15, 2012, 01:04:07 PM
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That's what I meant. We have "code" for Spartan 6, of course you "port" that on an Altera device first before you go the Altera route. And with "put" I don't necessarily mean upload and change a few lines Wink

$4k/each doesn't sound so bad, I suppose you only need one or two to create the prototypes and mine for a while to get them stable.

I would still be interested in the estimated price and lead time.
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March 15, 2012, 01:08:18 PM
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The first step would be getting an efficient design on a Stratix IV series chip.  There isn't much porting.  Bitstreams are very device specific.  You can get started in this stage for $10K plus an experienced FPGA engineer.

If/when you have an efficient design on a Stratix IV series chip lead time for a HardCopy is about 3-4 months and capital requirements will be in the $200K+ range.

It reamains to be seen if a HardCopy IV chip will be competitive on a MH/$ basis though.  A lot depends on how many MH/S you can get out of a Stratix.  Since Stratix is a dead end (nobody is going to be buying $5K miners which get <1 GH/s) unless you use it as a stepping stone to HardCopy a lot remains unknown (and thus risky).
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March 15, 2012, 01:14:07 PM
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Thanks a lot, you are really very knowledgeable in this field. Just out of curiosity, did you learn this through Bitcoin and mining, or is this some knowledge you acquired unrelated to Bitcoins?
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March 15, 2012, 01:25:33 PM
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Thanks a lot, you are really very knowledgeable in this field. Just out of curiosity, did you learn this through Bitcoin and mining, or is this some knowledge you acquired unrelated to Bitcoins?


Unrelated to Bitcoin.  At one time I worked for Juniper networks.  Some of the high end products use FPGAs and sASICs because volume is too low to make using ASICs cost effective.  I didn't do any FPGA programming BTW. 
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March 15, 2012, 01:58:01 PM
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Thanks a lot, you are really very knowledgeable in this field. Just out of curiosity, did you learn this through Bitcoin and mining, or is this some knowledge you acquired unrelated to Bitcoins?


Unrelated to Bitcoin.  At one time I worked for Juniper networks.  Some of the high end products use FPGAs and sASICs because volume is so low to make using ASICs cost effective.


@DandT.  Did you read that Cisco will be temporarily sourcing off the shelf silicon due to the pickle they have found themselves in with fractured product lines.  Lulz.  They don't know which front to fight on and with  what. Wink

(sorry for hi-jack)
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March 15, 2012, 02:02:00 PM
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Thanks a lot, you are really very knowledgeable in this field. Just out of curiosity, did you learn this through Bitcoin and mining, or is this some knowledge you acquired unrelated to Bitcoins?


Unrelated to Bitcoin.  At one time I worked for Juniper networks.  Some of the high end products use FPGAs and sASICs because volume is so low to make using ASICs cost effective.


@DandT.  Did you read that Cisco will be temporarily sourcing off the shelf silicon due to the pickle they have found themselves in with fractured product lines.  Lulz.  They don't know which front to fight on and with  what. Wink

(sorry for hi-jack)

I hadn't heard but after how they destroyed the awesome Linksys brand I can't say it makes me sad.  Hopefully CISCO can de-frak themselves and their product lines.  I mean it isn't rocket science and gross margins are 50%+.  How exactly you end up with products which don't talk to each other when you make both of them I am not really sure.
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March 15, 2012, 02:08:53 PM
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Thanks a lot, you are really very knowledgeable in this field. Just out of curiosity, did you learn this through Bitcoin and mining, or is this some knowledge you acquired unrelated to Bitcoins?


Unrelated to Bitcoin.  At one time I worked for Juniper networks.  Some of the high end products use FPGAs and sASICs because volume is so low to make using ASICs cost effective.


@DandT.  Did you read that Cisco will be temporarily sourcing off the shelf silicon due to the pickle they have found themselves in with fractured product lines.  Lulz.  They don't know which front to fight on and with  what. Wink

(sorry for hi-jack)

I hadn't heard but after how they destroyed the awesome Linksys brand I can't say it makes me sad.  Hopefully CISCO can de-frak themselves and their product lines.  I mean it isn't rocket science and gross margins are 50%+.  How exactly you end up with products which don't talk to each other when you make both of them I am not really sure.

As with most big companies bureaucracy creeps in and the company loses cohesion. The more high tech the company the worse the results.

IMO.

Actually, Juniper really has smart designs.  I mean, why else would the Federal Govt buy Juniper to span ports at major NAPs and funnel to the NSA...

Cheesy
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March 15, 2012, 04:06:41 PM
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Most i hate about Cisco switches is that every single model has somewhat different management commands/configuration ffs! :/

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Wandering Albatross
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March 21, 2012, 07:22:35 PM
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Updated

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March 22, 2012, 03:27:13 PM
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How much would going from Spartan 6 to Altera Hardcopy (and then to a board that actually plugs in to a USB port) be? And whats the estimated time to have these bad boys delivered to your door step?


Infinite. Smiley

Spartan = xilinx FPGA
Altera Hardcopy = Altera sASIC.

You would need a competitive FPGA using an Altera chip and not just any chip a chip that they have a HardCopy equivelent for.

Altera "Spartan equivelent" is the Cyclone and there is no path to HardCopy from a Cyclone.  You would need a Stratix family chip (and they start @ $4K ea).

do you have an educated guess as to what kind of hashrate one of those 4k chips could push?
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