I visited BFL, any questions ?

[eldentyrell]

Which FPGA chip are they using? (they say we can use it for other purpose, but at the same time they do everything to hide what it is from customers).

This is really easy to figure out.  Their board has an exposed JTAG header; just hook it up and query for the IDCODE.  I've offered a 5BTC bounty for whoever does this first.

[1714120245]

1714120245

[1714120245]

1714120245

[DeathAndTaxes]

Which FPGA chip are they using? (they say we can use it for other purpose, but at the same time they do everything to hide what it is from customers).

This is really easy to figure out.  Their board has an exposed JTAG header; just hook it up and query for the IDCODE.  I've offered a 5BTC bounty for whoever does this first.

BFL indicated that won't work.  My guess is the JTAG header is not connected directly to the chip.

[eldentyrell]

Which FPGA chip are they using? (they say we can use it for other purpose, but at the same time they do everything to hide what it is from customers).

This is really easy to figure out.  Their board has an exposed JTAG header; just hook it up and query for the IDCODE.  I've offered a 5BTC bounty for whoever does this first.

BFL indicated that won't work.  My guess is the JTAG header is not connected directly to the chip.

That sounds like BFL trying to discourage people from trying.  If the header weren't connected to anything, they wouldn't have wasted board space on it.  Also, not having a JTAG connection to the most expensive device on the board is a huge DFM (design for manufacturability) and DFT (design for testability) nightmare.

I'll still pay 5BTC for an IDCODE readout even if it turns out the "big chip" is not on the chain and all that comes back is some sort of flash memory device (e.g. for holding configuration data).

[Garr255]

I'll still pay 5BTC for an IDCODE readout even if it turns out the "big chip" is not on the chain and all that comes back is some sort of flash memory device (e.g. for holding configuration data).

I'm also very interested in this. Someone do it please!

[antirack]

What if they switched pins around on the JTAG header (not even sure if it is populated on the PCB, I won't bother to look at the pictures).

[ElectricMucus]

What are the chances of the BFL chips being a genuine Cell ASIC anyway?

I get the whole calling the bluff thing, but shouldn't it come up at digikey or mouser if you *just* select the right package and look in the price range? (What form factor is the package some VFBGAXXX, but which one?)

[abeaulieu]

What if they switched pins around on the JTAG header (not even sure if it is populated on the PCB, I won't bother to look at the pictures).

It's easy enough to figure out if someone would just probe the damn thing. lol
There are actually a surprising amount of JTAG configurations anyway.

[DeathAndTaxes]

The chip many of us guess it to be can't be purchased retail at the price point BFL is offering so the theory is that they secured are leveraging a significant discount to retail price.

As far as sASIC, Cell ASIC, Custom ASIC, etc.  It doesn't fit.
MH/W is horrible (relatively speaking). 
The board has a JTAG and a flash loader neither of which are used with xASIC.

[Inspector 2211]

The chip many of us guess it to be can't be purchased retail at the price point BFL is offering so the theory is that they secured are leveraging a significant discount to retail price.

As far as sASIC, Cell ASIC, Custom ASIC, etc.  It doesn't fit.
MH/W is horrible (relatively speaking). 
The board has a JTAG and a flash loader neither of which are used with xASIC.

It's not an ASIC built for mining, but a CONFIGURABLE ASIC, like an array processor or a custom FPGA.
That's why MH/W is "horrible" - it's not a chip built specifically for mining.
 
And yes, many, if not most ASIC designers do put a JTAG interface on the ASIC, to facilitate in-circuit testing.
For instance, via JTAG one can set any output pin to any value, thus allowing early production tests, whether the chip was soldered correctly etc.

[DeathAndTaxes]

Well calling a custom FGPA an ASIC kinda defeat the entire purpose of using standardized terms.

ASIC = "application-specific integrated circuit"

A customizable programmable application specific integrated circuit is kinda an oxymoron wouldn't you say?

occam's razor says it is a Stratix III FPGA (my total guess would be a EP3SL150F780) purchased at huge discount to retail price because the Stratix III is EOL.

The voltage, power draw, dimensions, pin layout, package type, voltage, and board characteristics (1MB flash loader, JTAG header, etc) all match that hypothesis.

[ice_chill]

Well calling a custom FGPA an ASIC kinda defeat the entire purpose of using standardized terms.

ASIC = "application-specific integrated circuit"

A customizable programmable application specific integrated circuit is kinda an oxymoron wouldn't you say?

occam's razor says it is a Stratix III FPGA (my total guess would be a EP3SL150F780) purchased at huge discount to retail price because the Stratix III is EOL.

The voltage, power draw, dimensions, pin layout, package type, voltage, and board characteristics (1MB flash loader, JTAG header, etc) all match that hypothesis.

So assuming it is that chip, if mining becomes unprofitable and BFL release a development SDK, will the hardware be worth good money ?

[Inspector 2211]

Well calling a custom FGPA an ASIC kinda defeat the entire purpose of using standardized terms.

ASIC = "application-specific integrated circuit"

A customizable programmable application specific integrated circuit is kinda an oxymoron wouldn't you say?

occam's razor says it is a Stratix III FPGA (my total guess would be a EP3SL150F780) purchased at huge discount to retail price because the Stratix III is EOL.

The voltage, power draw, dimensions, pin layout, package type, voltage, and board characteristics (1MB flash loader, JTAG header, etc) all match that hypothesis.

I disagree. Everybody makes ASICs now. Almost nobody (except Intel and IBM) can afford to make a full-custom chip anymore. The full-custom chip has gone the way of the dodo. Thus, a Xilinx FPGA is an ASIC. An Altera FPGA is an ASIC. A custom BFL FPGA is an ASIC.
I'd still call an Intel CPU a full-custom chip. Also an IBM Power7 CPU.
AMD? Not so sure, and it shows.
Oracle/SUN CPUs? More like an ASIC (manufactured by TI) than full custom.

Full-custom: Optimized at the transistor level.
ASIC: Run through Synopsys DC and some back-end tools, but not optimized at the transistor level.

>purchased at a huge discount



In books and movies, they call that "deus ex machina", i.e. some kind of wonder or act of god to resolve a problem in the plot, like a scientist being able to stop an impending alien attack with a computer virus which he uploads to the alien mother ship.

My theory does not require a deus ex machina.

[DeathAndTaxes]

Calling an FPGA an ASIC defeats the entire purpose of the definition.  Definitions exist for a reason.  
In related new I have a miner working with quantum computing*.  It's true.

* Quantum computing in this case doesn't refer to any commonly accepted definition of the word it refers HD 5970s.  Definitions? We don't need no stinking definitions.

Calling a FPGA and ASIC is asinine.  It is like deciding you are going to call floating point numbers, iinteger or the language the rest of the world knows as English, Spanish, or the period of time when the sun is down "daytime".

FPGA = Field Programmable Gate Array
ASIC = Application SPECIFIC Integrated Circuit.
The definitions are mutually exclusive.

Even if they weren't lets boil this down.  Your (accepted by nobody else on the planet) definition of an ASIC is so board as to include virtually all silicon chips?  Ok genius you honestly think it is a breakthrough that we "now" know that BFL uses Silicon chips.    Prior to that revelation I honestly thought they built their boards out of potatoes.   Thanks for that clarification.  What address should I tip you some coins.

[Inspector 2211]

Calling an FPGA an ASIC defeats the entire purpose of the definition.  Definitions exist for a reason.  

In related new I have a miner working with quantum computing*.  It's true.

* Quantum computing in this case doesn't refer to any commonly accepted definition of the word it refers HD 5970s.  Definitions who needs definitions.

Calling a FPGA and ASIC is asinine.  Utterly asinine.  It is like deciding you are going to call floating point integer or English spanish, or the period of time when the sun is down "daytime".

FPGA = Field Programmable Gate Array
ASIC = Application SPECIFIC Integrated Circuit.
The definitions are mutually exclusive.

Even if they weren't lets boil this down.  Your (accepted by nobody else on the planet) definition of an ASIC is a silicon chip?  Ok genius you honestly think it is a breakthrough that we "now" know that BFL uses Silicon chips.  Thanks for that clarification.  Prior to that I honestly thought they built their boards out of potatoes. 

A FPGA is a sub-category of an ASIC.
It's APPLICATION happens to be being a programmable chip.
What's so hard to understand about this?

A FPGA is not a full-custom chip because even large companies like Xilinx or Altera lack the financial resources to design full-custom chips. Not being a full-custom chip, it is an ASIC. Subcategory FPGA.
I hope this clarifies it.

[DeathAndTaxes]

A FPGA is a sub-category of an ASIC.
It's APPLICATION happens to be being a programmable chip.
What's so hard to understand about this?

A FPGA is not a full-custom chip because even large companies like Xilinx or Altera lack the financial resources to design full-custom chips. Not being a full-custom chip, it is an ASIC. Subcategory FPGA.
I hope this clarifies it.

No those are made up nonsense terms & definitions used by nobody except yourself. In the future if you wish to make up nonsense definitions it would be less confusing if applies them to new made up terms.

Like this:

A Flangerton is a sub-category of an Aderonk
It's Aderonk-ness happens to be being a pos-rogged clinkos.
What's so hard to understand about this?

A Flangerton is not a full-custom clinko because even large companies like Xilinx or Altera lack the financial resources to design full-custom clinkos. Not being a full-custom clinkos, it is an Aderonk. Subcategory Flangerton .
I hope this clarifies it.

[Inspector 2211]

A FPGA is a sub-category of an ASIC.
It's APPLICATION happens to be being a programmable chip.
What's so hard to understand about this?

A FPGA is not a full-custom chip because even large companies like Xilinx or Altera lack the financial resources to design full-custom chips. Not being a full-custom chip, it is an ASIC. Subcategory FPGA.
I hope this clarifies it.

No those are made up nonsense terms & definitions used by nobody except yourself. In the future if you wish to make up nonsense definitions it would be less confusing if applies them to new made up terms.

Like this:

A Flangerton is a sub-category of an Aderonk
It's Aderonk-ness happens to be being a pos-rogged clinkos.
What's so hard to understand about this?

A Flangerton is not a full-custom clinko because even large companies like Xilinx or Altera lack the financial resources to design full-custom clinkos. Not being a full-custom clinkos, it is an Aderonk. Subcategory Flangerton .
I hope this clarifies it.

If you tried to learn a little bit about how ASIC foundries like TSMC operate, where Xilinx and Altera and Nvidia, among others, have their chips manufactured, then you would know that each and every foundry customer has to follow a foundry-approved process to have their ASICs manufactured. These foundries are not interested all the back-and-forth that's involved in running full-custom chips through their foundries. If you own your own fab, like Intel does, different story. Don't try to cloud the issues, but educate yourself instead.

[gyverlb]

No those are made up nonsense terms & definitions used by nobody except yourself. In the future if you wish to make up nonsense definitions it would be less confusing if applies them to new made up terms.

I agree.
A minor part of the silicon in each FPGA behaves like an ASIC (the interfaces used to program the FPGA for example are probably fixed gates). Every general purpose ASIC (ie Turing-complete CPU+RAM) can emulate FPGAs. So you could argue that there's a blurry line between the two (but you can for nearly every 2 arbitrary concepts).
The difference is the technologies used to build FPGAs and ASICs and their respective strength : the programmable part in most FPGAs are implemented with SRAM tech to get the most efficient silicon structure capable of hardware reconfiguration. Most ASICs only uses SRAM for memory (cache usually), the rest is a fixed gate logic structure. So to say that FPGAs are ASICs is like saying that the interface used to program them which my represent less than 1% of the silicon and be used only a couple of times in its life defines it instead of the 99% of the silicon used most of the time. You could argue that a CPU is a memory chip with more success (given the quantity of silicon dedicated to caches...).

[Inspector 2211]

I'll explain it once again:
A buddy of mine is an ASIC designer here in Silicon Valley.
When asked to implement an FPGA on a standard ASIC design flow, he could obviously do that, have some other people in his company implement and verify the physical back-end and then ship the design files off to TSMC or some other foundry.

A few months later, you receive your first sample ASIC, which implements an FPGA.

There's no secret, magic FPGA design flow at TSMC, just like there is no secret, magic source for Stratix III chips at 1/10th of the list price.

[eldentyrell]

What if they switched pins around on the JTAG header

Meh, perhaps.

OTOH JTAG only uses four wires, so trying every permutation shouldn't take long.

(not even sure if it is populated on the PCB, I won't bother to look at the pictures).

It wasn't.  But the part is like $0.15 from digi-key and it's through-hole so soldering it is a walk in the park.  If you're afraid to solder down the header you can just use probe clips.

[eldentyrell]

I get the whole calling the bluff thing, but shouldn't it come up at digikey or mouser if you *just* select the right package and look in the price range? (What form factor is the package some VFBGAXXX, but which one?)

The packages aren't really standardized; each manufacturer has their own names for them.  The only thing that's quasi-standard is the ball pitch.  Also some have suggested that BFL is using an older Stratix device, which I'm sure DigiKey/Mouser no longer carry.  Finally, DigiKey+Mouser don't always carry every packaging style for every chip.