Bitcoin Forum

This thread shall be used to report the best demonstrated energy efficiencies of real-world ASIC implementations of SHA-256 at the chip level.

• 1290 Mhash/Joule claimed by bitfury at the chip level, and 1140 Mhash/J (https://bitcointalk.org/index.php?topic=228677.msg2796663#msg2796663) were confirmed by cscape at 12V.
• 310 Mhash/Joule as reported by BFL on their 65nm ASIC (they document 3.2 Watt per Gh/s (https://products.butterflylabs.com/homepage-subproducts/65nm-asic-bitcoin-mining-chip.html)).
• 167 Mhash/Joule as reported by Bitfountain/ASICMINER/friedcat when measuring power consumption on their Block Erupter 130nm ASIC (https://bitcointalk.org/index.php?topic=99497.msg1571278#msg1571278) (down to "6 Watt per 1 Ghash/s"). At 12V DC their implementation's efficiency is 130 Mhash/Joule (each 10.752 Gh/s blade consumes 83 Watt (https://bitcointalk.org/index.php?topic=178275.0)). Note that previous RTL simulations (https://bitcointalk.org/index.php?topic=91173.msg1215501#msg1215501) had estimated 238 Mhash/Joule at the chip level.
• 151 Mhash/Joule for the 110nm Avalon, as advertised by the vendor saying 6.6-6.7 Watt per Ghash/s (https://bitcointalk.org/index.php?topic=139704.msg1487845#msg1487845) and as confirmed by real-world measurements (620 Watt at the wall but 438 Watt consumed by the chips after removing AC/DC and DC/DC PSU inefficiencies (https://bitcointalk.org/index.php?topic=95762.msg1499382#msg1499382)).
• 73 Mhash/Joule derived from "13.76 mJ/Gbits" as measured on a 130nm ASIC developed by a research group from Virginia Tech for comparing SHA-256 to SHA-3 candidates: http://rijndael.ece.vt.edu/sha3/publications/DATE2012SHA3.pdf (pub. March 2012). RTL simulations preceding the manufacture of the chip had predicted a number very close to this: 13.42 mJ/Gbits.

(Note: for reference, hashing 1 gigabit of data per second corresponds to a mining speed of about 1 Mhash/s because one Bitcoin hash consists of hashing 1024 bits of data, or 2 SHA-256 data blocks: SHA-256(SHA-256(x)) minus a few SHA-256 steps that can be optimized out.)


BFL claims the 'SC' Jalapeno (3.5 Ghash/s) will be USB-powered (https://bitcointalk.org/index.php?topic=87934.msg1075223#msg1075223). I theorize it will draw 5W via 2 USB ports (https://bitcointalk.org/index.php?topic=95762.msg1057667#msg1057667) (2.5W per port), giving it an efficiency of 700 Mhash/J. Edit: BFL has since then confirmed that the Jalapeno will be powered by 2 USB ports.

The 167 Mhash/J number at 130nm indicates that 668 Mhash/J should be possible by merely scaling down the design to 65nm (because 65nm is theoretically 4x more power efficient than 130nm as efficiency is linearly proportional to the transistor junction area), confirming my BFL estimate of 700 Mhash/J. Furthermore, it is known that BFL pre-sold $250k of SC devices in the first day (http://bit.ly/LyEOx0), making it almost certain that they can cover the NRE cost for developing at 65nm which is only $500k (https://bitcointalk.org/index.php?topic=91173.msg1003326#msg1003326). (And on top of pre-order revenues, BFL also claim to have received VC capital.)

Blah, BFL is talking about ~1750MH/Joule ;) Jalapeno, USB device 3.5GH/s @ 2W from USB ;)

I know. (Actually 1400 Mhash/Joule at 2.5W.) And the goal of this thread is to compare BFL's theoretical claims vs. actual chips.

Let me get this straight: BFL is claiming 1,750 MH/J and you are trying to say that is plausible based on some paper you found that demonstrated 71 MH/J?

Seriously?

Let me ask you this: if the chip measured 13.76 mJ/Gbits at 130nm, what do you think is a plausible mJ/Gbits performance figure at 32nm? how about 45nm?

If you are just looking for best Mhash/Joule I'll downclock my intel Q6600 from 2.4GHz to 2.4MHz so it is 1000 times slower and uses 1,000,000 times less energy so it gets a 1000 times better MHash/Joule rating.

Except you just increased your cost per Mh/s by a factor 1000x.

This is why GPUs cannot compete with FPGAs even when underclocked/undervolted. Because you still pay full price and end up running the hw at a fraction of the speed it is capable of.

So you should add to the question the minimum hashrate for a chip.
But you don't know yet how many chips BFL is using in the new products.

Shouldn't this be in mining speculation?

I find it tedious that these types of discussion can even continue. There are only 2 probable outcomes: BFL meets their stated specs, which are incomplete or they fail to get what they sold everyone on.

nuff said.

A quick note, it should be confirmed (I haven't the time to read it directly) if this article is talking about MHash/s as in SHA256 Hashes, or MHash/s as in Bitcoin hashes... Remember, a single Bitcoin Hash is 2x SHA256 Hashes... Meaning 1200MHash/s in raw SHA256 Hashes is actually only 600Mhash/s in bitcoin speak.

Neither. It talks about SHA-256 speed in Gbit/sec. See "Note 1" in my first post.

And everyone is 100% sure they aren't going to have an external power supply? A small wall wart?

USB 3 is 4.5 W

I think you need to go the other way start at what a US based 20 AMP 120V power plug could supply and work backwards using the 1 THash box.

15 AMPs * 120V == 1800 watts, 80% eff would give 1,440 watts available.

~695MH / Watt

Jalapeno is going to need a wall wart mystery solved?

Or Jalapeno will be downclocked and downvolted a little bit to met USB specs. Mystery solved? We may speculate till dawn....
My guess is just like that: Single chip is designed to deliver 4GH/s @ 4W. SC Single will contain 10 of this chips, Mini rig 250. Jalapeno downclocked and downvolted to 3,5GH @ 2,5W.

Y Cable, like some harddrives?

Maybe it'll be 3.5Gbit/s per chip?  ;D Maybe they had a "misunderstanding".

BFL confirmed (in a thread around here somewhere) that the Jalepeno would run off of the USB port as it's power source, and that it would not require USB 3.0.  Of course, until it actually happens, I'd still call that speculation, but it is at least BFL's goal to have it run only on the USB power alone.

ITT: People graciously try figuring out how BFL could possibly make good on their ASIC promises by putting them on par with the best MH/J rate and best W/die size rates currently known in the research field (which usually takes 3-10 years to materialize into products if it comes to fruition at all).

Dude... 65, 45, and even 35 nm are far from experimental. 22nm is current, and we aren't even looking at those numbers, although they would have great performance.

28nm theoretical Mh/W have been tossed around. Very rosy to think BFL has a VC source willing to pony up 10s of millions up front for that kind of chip development. IMO, given the Bitcoin market 65nm makes the most sense with 45nm, better odds if it's a FPGA->ASIC copy, being an outside possibility.

And the SHA design in OP is definitely experimental/research.

What I meant was that the processes are mature. As long as you have a good designer, you aren't going to have any issue getting them fabbed. Thus my comment about whether or not it was "experimental".

No, they explicitly said it was "USB powered".  What you describe is "wall wart powered".

I see, but even so implementing this research core in any form at a higher MHz target and larger die (more SHA units) would be cutting edge R&D especially with 28nm which even major companies are supply constrained on.

If BFL is producing a full custom chip on a 32nm node I will liquify my hat in a blender and eat it. I could see 65nm, but anything lower would be a stretch. AMD and NVIDIA just left the 40nm node this year, and AMD and GloFo is still producing their CPUs on 32nm.

Quoted for the lulz, even though I agree.

BFL is "a market leader in microprocessor design", so they're clearly on par with AMD and Nvidia. I expect BFL will use 28nm.

1440W is a good assumption! This number matches almost exactly my OP which estimates the Jalapeno at 700 Mh/Joule by using 2 USB plugs for power.
This 700 Mh/Joule number makes so much sense that it has become my best bet as to what the SC product line will produce.
700 Mh/Joule is even doable at merely 45nm per my OP.

• Jalapeno SC: 5W via 2 USB plugs, 3.5 Ghash/s -> 700 Mhash/J
• Single SC: 57W, 40 Ghash/s -> 700 Mhash/J
• Mini Rig SC: 1440W, 1 Thash/s -> 700 Mhash/J

BFL's claims are plausible at 45nm, not 28nm. See post above.

Best guess:
50 chips of 20 Ghash/s each in the Mini Rig
2 chips of 20 Ghash/s each in the Single
1 "small" chip of 3.5 Ghash/s in the Jalapeno which has roughly 1/6th the die size (therefore 1/6th the performance) of the other chips

Wouldn't this require 2 separate mask sets etc. which would produce 2 times NRE cost?

It's plausible they will achieve perfect MHz, die scaling, and process shrinking improvements on a university research design (Published in March of this year no less)? That their identity-less VC backer will pony up the money to develop a full ASIC design on 45nm. We're talking R&D on 45nm, multiple wafer tests would be expected. Oh yeah this is plausible...

The university design is likely imperfect.  I bet engineers with years of experience can make it happen with even greater efficiency.

And yeah, you can bet your bottom that any VC with any sort of investment fortitude would be willing to put down whatever dollars are required to finish this after seeing BFL take in millions of dollars without even having a product to show for it yet.

Source?

I really think many are over estimating what a 45nm ASIC is capable of. It certainly won't do what many are suggesting aka BFL stated numbers.
A 22nm or at a push a 28nm might, but it will massively depend on their design which is far from perfect. All the FPGA's on the market including BFL's still have not reached their ceiling limit, so I don't expect them to be pushing an ASIC to it's limit either.

I don't say this flippantly, my dad (him far more than I) and I, have done a lot of encryption based projects, involving FPGA's and ASIC's. He has always focused on hardware, myself more software based.
ASIC are fantastic chips if you can afford the upstart costs, however FPGA's have advanced to a point that they are fast enough that they are being used as the first choice, instead of ASIC.

The original poster brings up accurate statistics, I'm sure they can make a USB powered ASIC, I've used both FPGA's and ASIC that run on those sort of wattage before, they can do a lot, especially the ASIC, but they can't do a double-SHA-256 as frequently as they say.
I estimate the 2.5 watt (coffee warmer) will likely only do 1000 Mhash/s, A long way off their 3500 Mhash/s Statement.

Do you think that Intel having, say, 5 different combinations of core counts, cache size, etc for their Sandy Bridge processors, mean that they incurred 5x the NRE costs to develop them?

No.

They take pre-designed logic blocks (cores, cache, etc) and can mix and match them relatively easily to produce a die with specific characteristics. The few cases where different SKUs are built on the same design (eg. a 3-core CPU made from a 4-core die) allow processor manufacturers to keep a stock of the same die, and "brand" them on-the-fly to match market demand (so that they don't get stuck with unsold 4-core inventory and production capacity when the markets buy 3-core).

For the same reason, BFL designing 2 different dies will not double their NRE cost. It makes sense for a Bitcoin ASIC to be made of the same hashing logic block duplicated dozens/hundreds of times across the die (see the "sea-of-tiny hashers" design made by bitfury -- the same applies to FPGAs). Therefore there is almost zero engineering effort and cost in taking a working die with, say, 60 hashing blocks, and deciding to produce a smaller die with only 10 hashing blocks.

This is math. Power consumption varies with the square of the feature size. So when comparing a chip designed at 45nm to a 130nm version of it running at the same frequency and same voltage, there should be a 8x better power efficiency: (130/45)**2 = 8.3

Ask your dad, he will tell you that for 2 identical designs, power consumption will vary proportionally to the transistor junction area.

It's not anywhere near double but the costs of masking and producing are still there, unless they plan on disabling lots and lots of blocks off one larger die (this is what Intel and AMD do for some of their chips).

I'm aware of the mathematics, the math of scaling does work like that. But it's not the only math that effects the final outcome.

However you have also made a convenient assumption that it will utilise two usb ports to power it, allowing it to have twice as much power, for a max of 5 watts. That is abit of a stretch to assume that and why the math to me does not add up for it to do 3.5 Gh/s at 2.5W and is what I stated.
2.5W is also something an ASIC could easily run off, it would not need to rely on 5W to work fully. 5W might allow it to go that bit higher, but I still think it be off by a bit of course.

Their FPGA to ASIC conversion and how efficiently they move that over will matter the most, since few are doing the same sort of double hashing, so it's not like they can just copy or modify the design of someone elses.

Power doesn't usually turn out ideally on these die shrinks though. Otherwise instead of Atom cpus Intel would have a sub Watt Pentium 3 1GHz die at 32nm.

I love when I get to dust off the cobwebs..

Pentium M was the mobile processor that all current out-of-order Intel desktop/server chips are based off of. Pentium M was a Pentium 3 core with some spruced up I/O. Pentium M led to Core Duo(yonah), which were holywtf awesome at the time, which then lead to Core 2 Duo(conroe) which then lead to the 45nm shrink(penryn). That then lead to the architecture improvement that was nehalem, which lead to the 32nm shrink that was westmere(with the awkward clarkdale phase), which lead to the architecture improvement that was sandybridge, and then the 22nm shrink that is ivy bridge.

If Intel wanted, they could sell a sub-watt single core Ivy Bridge chip. But instead they chose to butcher their core, remove the out of order components, and trick the market in to needing a second core that costs them next to nothing to manufacture. You have to give them credit as they effectively established a tablet-like market with the netbooks based off early Atom processors.

...and they do:

0.65W Atom Z500 with twice the cache than the Pentium III, more instructions supported (SSE2, SSE3), twice the threads, not 1GHz but close: 800MHz (because it is not 32nm, but 45nm): http://ark.intel.com/products/35472

Or look at this one:
1.4W Atom Z600 with twice the cache, SSE2, SSE3, twice the threads, and 1.2GHz: http://ark.intel.com/products/49656

What do you think Atom CPUs are? They are built upon the Pentium III/M design. Yeah they don't support OOO execution for whatever reason (artificial market segmentation between Atom and higher-end CPUs, or making TDP room for supporting things Intel deemed more important such as 512kB cache, SSE2, SSE3, etc), but they pretty much prove that a sub-Watt (at 32nm) or ~1.5W (at 45nm) Pentium III core is possible.

http://www.cpubenchmark.net/cpu_lookup.php?cpu=Intel+Atom+Z510+%40+1.10GHz

http://ark.intel.com/products/35469/Intel-Atom-Processor-Z510-%28512K-Cache-1_10-GHz-400-MHz-FSB%29

http://ark.intel.com/products/31855/Intel-Pentium-III-Processor---S-1_00-GHz-512K-Cache-133-MHz-FSB

Z510 is a bit slower than mobile P3 1GHz, 130nm->45nm no performance increase but 16.5% of the power use. Keep in mind this is Intel the biggest chip foundry in the world.

The round "2 W" number quoted for the Z510 is likely Intel rounding up.
Compare instead the (faster) 1.3 W Z600 which I linked above.
130nm->45nm predicts a reduction of the power to 12% (1/8th), and the Z600 reduces it to 11%, hence proving my point.

Which still brings us back to.


And keep in mind that's Intel showing that there is no free performance bonus when aiming for power reduction, are we seriously going to armchair ref that BFL is on par with Intel in terms of engineering and chip production?

I have explained many times I think they will do 700 Mh/J, not 1750 Mh/J. Read this thread.

Using a 2012 research chip design? If they pull that off then they should just become a chip design firm because it'll mean they have some of the best engineers in the world.

My point, and rjk's point is that: What makes you think the authors of that paper are the world's best ASIC designers? They are not. They are students and professors. The bleeding edge of ASIC research happens in the professional world (at TSMC, Intel, etc), not in the academic world.

The authors did not need to be excellent ASIC designers to conduct this research. They merely tried to make an average design, and that's all they needed to fairly compare the efficiency of different hash functions. This was all they needed to reach their research goal.

That team achieved 71 Mh/J at 130nm, using standard-cell tech. The true best ASIC designers would have achieved higher that that, using full-custom tech not standard-cell, and would have demonstrated it on a smaller process node like 45nm.

PS: the Virginia Tech researchers did not even do the VHDL design themselves, they implemented the one from GMU: https://cryptography.gmu.edu/athena/index.php?id=source_codes  It looks like it is https://cryptography.gmu.edu/athena/sources/2011_10_01/basic/SHA-2_basic.zip  -> any half-decent ASIC designers should be able to take it, implement it to 45nm standard-cell tech, and get 700 Mh/J

I guess this 1+ Billion market cap company is slacking.

http://www.cavium.com/processor_security_nitrox-III.html

20W 30Gbps SHA2

Apples vs. Oranges.

Nitrox III implements much more than SHA-2: full-blown RISC cores, RSA acceleration, etc, blowing its TDP up.

30Gbps corresponds to 29 Mhash/s. At 20W that's 1.45 Mhash/J. Nitrox III is handily beaten by all the Spartan 6 FPGAs around here doing 20 Mhash/J. Why were you thinking that Calvium's chips were the "state of the art" in SHA-2 performance?

They are much bigger than BFL.  ::)

Maybe you should tip Cavium that by taking an open source SHA-2 VHDL design from students/professors, and implementing it on a 12-year-old 130nm design, they could increase their energy efficiency by a factor 49x from 1.45 Mhash/J to 71 Mhash/J.

My point is: obviously Cavium did not aim at SHA-2 energy efficiency. You are comparing Apples vs. Oranges.

Or possibly reaching that energy efficiency at higher clocks *and variable protocol settings is not easy. I don't see why they wouldn't want a well balanced SHA2 logic block in their design.

I gave you the answer already: what is consuming the bulk of their 20W power is the other logic blocks such as the RISC cores, RSA engines, etc. That's why comparing such a complex chip like the Nitrox III to a barebone SHA-2 logic block is a pointless apples vs. oranges exercise.

But if that's a 65nm or 45nm chip and the SHA2 block is allocated 1W of the power budget, shouldn't they be pulling 100+ MH/s? They better hire BFL stat.

Do you really think that BFL would be able to raise the capital necessary to do a full custom 45nm design? I could see maybe something like American Semi's 1D 45nm process, but to do a standard 45nm full custom design just don't make sense given the market. Between late 2012 and the start of 2015 there might be 3M BTC produced. Over two years is forever in Bitcoin terms, and it might take that long for them to recover the millions in NRE.

They are (supposedly) going to be the first to market with an ASIC. Why would you attempt to fabricate on something like 45nm which is still a modern process (the A5 and Exynos 4210 in the Galaxy SII are 45nm) and pay millions in NRE? If you design at 90nm, you could still destroy the competition and sell at basically the same price points, but the NRE would be a fraction of what you'd pay at 45nm. Your time to recover those expenses would be much smaller, and your all around risk would be much lower. If later on competitors force you to a newer process you're in the driver's seat; well funded, experience and with significant brand equity.

I just can't wrap my head around them doing something like that.

I said standard cell, not full custom:


And TSCM launched their standard-cell 45nm toolkits 5 years ago! As said earlier in this thread, this is hardly "bleeding edge" tech... The NRE costs are mostly proportional to the complexity of the chip you are designing. This is why dead-simple logic blocks (SRAM cells, NAND, etc) are always the first ones to be built at the smaller nodes (eg. 22 nm), whereas complex chips like the A5 lag behind (45 nm). A dumb SHA-256 logic block is much closer to SRAM/NAND in terms of complexity than a SoC like the A5. So I think BFL doing 45nm is absolutely plausible. But again, as I said in the OP, they may even get away with 65nm.

No because if you read the specs of the thing you found with 30sec of googling around, you would see the Nitrox III appears to run SHA-2/RSA/etc on RISC cores (ie. a CPU core), which implies it is not a custom SHA-256 ASIC, which explains its poor performance per Joule (after all, if it was an ASIC, it should beat Spartan6 FPGAs, but it does not.)

Accelerators mean there are at least some custom blocks for crypto in there. I'm going to side with you and say they are just terrible engineers and couldn't find a way to get 100MH/J equivalent out of their reserved SHA2 resources. That or they reserved just a few thousand transistors for SHA2 because having the best in class performance should be reserved for real winners like BFL.

If that's the case then BFL would be straight lying, as they've claimed that their design is full custom.

Have you considered the fact that SHA-2 in THEIR application may not require the ultimate in efficiency and even speed? 30Gbps is smoking fast for most SHA-2 applications outside of Bitcoin, and 20 watts is comparatively low-powered. I'm sure they see no reason to spend hundreds of man-hours on optimizing a small part of the overall chip design when the application that it is intended for is bottlenecked by other unrelated factors.

For those who are not following Block Erupter: Dedicated Mining ASIC Project (Open for Discussion) (http://"https://bitcointalk.org/index.php?topic=91173.msg1062854#msg1062854")

Fixing the url for you. Interesting numbers at 130nm, very promising as well for the future of ASIC development.
So If it was shrunk down to 45nm it would energy wise (optimal) result in a saving that result in about ~2 Watt chip, that does 1.25Gh/s.
Guess I wasn't that far off, when I estimated 1Gh/s for a single usb powered Chip based on a 45nm design. Still estimates, but at least an estimate I could believe.

More precisely, scaled to 45nm, Bit Erupter's chip would give 1.96 Ghash/s at 2.5 Watt.
This is 787 Mhash/sec and slightly better(!) than my prediction of 700 Mhash/sec for BFL's ASIC.

If BFL uses standard cell, I think they would have to go with 45nm to have chance to meet their spec.
What is the mask cost of 45nm these days?

But I figure they will go with a 45nm multiple wafer run, ie several designs on one wafer to cut down the initial cost.
They will quickly  get delivery problems but now they have proven their product.
I guess the next step is to get enough preorders by then to cover the cost of a full mask set.

It would not be a good idea to run a chip at 2.5 watts, a bit below 2 watts is a lot wiser, when a usb slot variance can easily dip below 2.5 watts.
Also the chip alone is not the only thing which will be drawing power, you have to take that into account, hence why the design should be below 2watts.

Only reason why your prediction "fits" is because you just assumed they'll be using 2 usb ports to power it and also apparently going over the spec of those usb slots are capable of providing.

Spec says 500mA, so you can draw 500mA. There is no such thing as "slot variance"; you are making that up...

You would be a pretty bad designer if you needed 0.5W or more to merely power ancillary logic. At most there will be a ~5-10% loss due to the 5V->Vcore power conversion (I doubt the ASIC will run on 5V). The rest (LED) should literally need 0.05W or less. Remember there is no active cooling (it's a coffee warmer). So we are talking about 2.3-2.4W available to the chip.

The USB 1.x and 2.0 specifications provide a 5 V supply on a single wire from which connected USB devices may draw power. The specification provides for no more than 5.25 V and no less than 4.75 V (5 V±5%) between the positive and negative bus power lines. For USB 3.0, the voltage supplied by low-powered hub ports is 4.45–5.25 V.

The usb spec, has a 5% variance. That is what I mean. But I won't be continueing in this thread anymore since you clearly taking this very personal to start attacking me for my opinion.

I read you too quickly (my bad) and thought you meant 0.5W/2.5W = 20% was the variance. I was denying this.

Yes, ±5% is quite typical for a consumer electronics power spec, and should be implied in all the numbers I quoted, and does not change my point (787 Mhash/J ±5% is still greater than 700 Mhash/J).

The Block Erupter 130nm project now claims an estimate of 122 Mhash/Joule: https://bitcointalk.org/index.php?topic=91173.msg1072887#msg1072887

This is such an improvement, that ~500 Mhash/Joule should be possible at 65nm. Combined with the fact that BFL disclosed that Jalapenos will be wall-powered (https://bitcointalk.org/index.php?topic=87934.msg1074756#msg1074756), after all, I think this makes it very, very likely that BFL is developing at 65nm and not 45nm.

OP updated.

Argh. OP updated again.

Just what I want, EXTRA heat right on top of my electronics!

Maybe OP could be updated with ngzhang's claim of "Avalon" simulation:

https://bitcointalk.org/index.php?topic=110090.msg1200284#msg1200284

160W for 60 Ghash/s ~ 375 Mhash/Joule

this is only a simulation, maybe a big difference between this and the final product.
after the post-simulation, we will have a  much accuracy power value.

See Lethos, I was right. I correctly predicted 3 months ago that it would use 2 USB ports, and BFL confirmed it:

Yep, it's in the prototype photo 1 USB + 1 mini USB (so you don't mix them up one presumes)

http://bitcoinmagazine.net/wp-content/uploads/2012/10/Jalapeno-Prototype-980x1024.png

I was right. One. More. Time. I correctly predicted 65nm and BFL confirmed it (http://bitcoinmagazine.net/bfl-confirms-65nm-process-for-sc-lineup/).

That has been my assumption as well, though I probably got the idea from you mrb.

mrb: What are your thoughts about the bASIC line using a little less than 2x the power per GH/s of the BFL SC line? You'd expect a 90nm chip to use twice the power of a 65nm chip all else being equal, right? Then what did BFL gain by going full custom? Shouldn't the BFL be significantly more efficient than 2x?

The bASIC power consumption estimate from Tom "8-10 devices per 1000W PSU" is too vague to make a statement at this point... For starters he did not say if he was talking about 24Ghash/s or 57Ghash/s devices.

I think it was a couple days ago that he clarified he meant the 54 GH unit, and in the last day he stated more directly that the 54 GH unit should use 100-120w, and the 27 GH unit 50-60w.

https://www.btcfpga.com/forum/index.php?topic=4.msg132#msg132

Ok. Assuming 120W for the 54 Ghash/sec device, that's 450 Mhash/Joule at 90nm.
Therefore Tom's standard-cell ASIC should in theory scale to 450 / ((65**2)/(90**2)) = 863 Mhash/Joule at 65nm.
If Tom went further and made it full custom, he would need a mere extra 16% efficiency gain to match BFL's 1000 Mhash/Joule.
But I would assume that making it full custom would have a lot more potential than a +16% efficiency gain.

So it seems:
- (1) either Tom's power efficiency estimates are optimistic
- (2) or BFL's power efficiency estimates are pessimistic
- (3) or BFL's full custom design has not been that well optimized after all
- (4) or Tom's standard cell design is extremely well optimized for being standard cell tech

I would say (4) is very likely since he hired state-of-the-art ASIC design firms. Knowing he had a very well optimized implementation would also explain why he initially did not believe BFL's 1000 Mhash/s claim as he probably assumed they were using std cell tech, and 65nm std cell tech should only be capable of 863 Mhash/Joule.

Time to refresh this thread. Avalon demonstrated 150 Mhash/Joule. This is twice better than the second best chip, developed by Virginia Tech, achieving 73 Mhash/Joule (obviously not Bitcoin-optimized).

Did Jeff post power consumption numbers somewhere?

No, Jeff did not. However Yifu quoted a very narrow range of 6.6-6.7 Watt per Ghash/s. So presumably he measured this on a real Avalon. I am sure Jeff will confirm soon.

https://bitcointalk.org/index.php?topic=140539.msg1497042#msg1497042

OP and title need to be corrected: It's closer to 100MH/s/J. It seems that Avalon uses 620w, not the 400W they've been claiming.

Holy. That is not what I was expecting at all. Has Avalon said whether they're using a standard cell or structured ASIC?

See ngzhang's post (https://bitcointalk.org/index.php?topic=140539.msg1497127#msg1497127) here before updating.

Consider PSU efficiency etc.

That is taking into account PSU inefficiencies. But that's an excuse for false advertising.

Alright, jgarzik measured 620 Watt at the wall. And taking into account ngzhang information, we determine that the power consumed by the chips is:

(620 (Watt at the wall) * .82 (AC/DC PSU efficiency) - 5 (Watt minimum for the fans)) * .87 (DC/DC PSU efficiency) = 438 Watt

At 66.3 Ghash/s, that is 66300/438 = 151 Mhash/Joule. So this confirms ngzhang's original claim of 6.6-6.7 Watt per Ghash/s for the chips.

Which is just idiotic.  Why is the standard now "at the chip".  We have been measuring MH/J since CPU days and never once has anything been measured "at the chip".  Is the miner going to pay "at the chip" electrical rates?

I mean say Avalon releases a version 3 with even WORSE DC/DC regulator which is only 70% efficient thus making the cost to operate 20%+ higher will that still be viewed as 151 MH/J.  FPGA custom boards were measured at the wall.  Why suddenly the change in metrics now?

I agree that miners should look at the consumption at the wall to calculate their real cost. But the purpose of this thread, my thread, is to compare consumption at the chip level.

And FYI, FPGA board vendors don't talk about power consumption at the wall, but at the 12V level, after the AC/DC PSU.

At the UPS socket not wall, to be specific.

One thing to keep in mind while interpreting BFL schedule performance and customer communication about schedule:

BFL's FPGA power consumption figures are at the wall; you can get better-than-quoted power usage by using a more efficient PSU. As far as I know, the only vendors that measure power consumption at the 12V input are the ones which make you supply your own PSU. Icarus had both options and gave both power consumption stats:

Also, all FPGA vendors which reported board-level power consumption did so for the whole board including power wasted in the onboard DC-DC converters, not the chip power usage as Avalon is doing. It's not like you can really unsolder the chips and put them in your own board with more efficient power circuitry, after all!

Updated OP with ASICMINER's 167 Mhash/J number.

Wanna update BFL's numbers too? Latest is ~170MH/J (https://forums.butterflylabs.com/bfl-forum-miscellaneous/1811-reason-behind-luke-jrs-asics-improved-performance.html#post24151).

yea, when they ship...

ASICMINER's auction of a 10.75GH/s blade claims 83W, including the DC/DC conversion. That gives 130MH/J not inclusive of the AC/DC conversion to be compared with Avalon's 151MH/J. The 167MH/J is therefore most likely just the chips, which agrees with Friedcat's claim that just the chips are between 6-8J/GH depending on voltage and clock speed.

That still makes ASICMINER a little more efficient design than Avalon, as 151MH/J * (110/130)^2 is 108MH/J.

The thread title is "shipped efficiency" or "demonstrated efficiency"?
If "shipped", ASICminer hasn't shipped yet as well. Apart of dividends, no one received a unit yet.

Thanks for the notice guys. Note that all my numbers are at the chip level. I added to the OP:

~230 Mhash/Joule (NOT FINAL) as estimated from BFL's 65nm ASIC prototype. They claim 170 Mhash/Joule at the wall. Both Avalon and Bitfountain/ASICMINER/friedcat lose ~25% of the power in AC/DC and DC/DC conversion and other elements, so if BFL experiences a comparable loss, we can infer 170/.75 = ~230 Mhash/Joule at the chip level.

I will update the thread title once the number is final.

Updated best result by bitfury's 55nm chip (1290 Mh/J at chip level!) This is roughly 65x more efficient than BFL's 40nm (Stratix II) FPGA-based Mini-Rig (20 Mh/J)!

Some people said a year ago that such then theoretical improvements would be plain absurd (https://bitcointalk.org/index.php?topic=92268.msg1017883#msg1017883) - well bitfury proves them wrong...

We just released a rev2 of our chip :) It would be nice to have this topic updated with latest info!

Bump. Let's see some updates. Energy efficiency is starting to become a factor in profitability.

Sure, what are your Mhash/Joule numbers?

PS: sorry I have not been monitoring this thread for a while.

Can we have all the numbers also shown as J / GH?
It's a more common measurement these days.