Best demonstrated efficiency: 1290 Mhash/Joule

[mrb]

This thread shall be used to report the best demonstrated energy efficiencies of real-world ASIC implementations of SHA-256 at the chip level.

• 1290 Mhash/Joule claimed by bitfury at the chip level, and 1140 Mhash/J were confirmed by cscape at 12V.
• 310 Mhash/Joule as reported by BFL on their 65nm ASIC (they document 3.2 Watt per Gh/s).
• 167 Mhash/Joule as reported by Bitfountain/ASICMINER/friedcat when measuring power consumption on their Block Erupter 130nm ASIC (down to "6 Watt per 1 Ghash/s"). At 12V DC their implementation's efficiency is 130 Mhash/Joule (each 10.752 Gh/s blade consumes 83 Watt). Note that previous RTL simulations had estimated 238 Mhash/Joule at the chip level.
• 151 Mhash/Joule for the 110nm Avalon, as advertised by the vendor saying 6.6-6.7 Watt per Ghash/s and as confirmed by real-world measurements (620 Watt at the wall but 438 Watt consumed by the chips after removing AC/DC and DC/DC PSU inefficiencies).
• 73 Mhash/Joule derived from "13.76 mJ/Gbits" as measured on a 130nm ASIC developed by a research group from Virginia Tech for comparing SHA-256 to SHA-3 candidates: http://rijndael.ece.vt.edu/sha3/publications/DATE2012SHA3.pdf (pub. March 2012). RTL simulations preceding the manufacture of the chip had predicted a number very close to this: 13.42 mJ/Gbits.

(Note: for reference, hashing 1 gigabit of data per second corresponds to a mining speed of about 1 Mhash/s because one Bitcoin hash consists of hashing 1024 bits of data, or 2 SHA-256 data blocks: SHA-256(SHA-256(x)) minus a few SHA-256 steps that can be optimized out.)


BFL claims the 'SC' Jalapeno (3.5 Ghash/s) will be USB-powered. I theorize it will draw 5W via 2 USB ports (2.5W per port), giving it an efficiency of 700 Mhash/J. Edit: BFL has since then confirmed that the Jalapeno will be powered by 2 USB ports.

The 167 Mhash/J number at 130nm indicates that 668 Mhash/J should be possible by merely scaling down the design to 65nm (because 65nm is theoretically 4x more power efficient than 130nm as efficiency is linearly proportional to the transistor junction area), confirming my BFL estimate of 700 Mhash/J. Furthermore, it is known that BFL pre-sold $250k of SC devices in the first day, making it almost certain that they can cover the NRE cost for developing at 65nm which is only $500k. (And on top of pre-order revenues, BFL also claim to have received VC capital.)

[Dexter770221]

Blah, BFL is talking about ~1750MH/Joule Jalapeno, USB device 3.5GH/s @ 2W from USB

[mrb]

I know. (Actually 1400 Mhash/Joule at 2.5W.) And the goal of this thread is to compare BFL's theoretical claims vs. actual chips.

[eldentyrell]

Let me get this straight: BFL is claiming 1,750 MH/J and you are trying to say that is plausible based on some paper you found that demonstrated 71 MH/J?

Seriously?

[mrb]

Let me ask you this: if the chip measured 13.76 mJ/Gbits at 130nm, what do you think is a plausible mJ/Gbits performance figure at 32nm? how about 45nm?

[pieppiep]

If you are just looking for best Mhash/Joule I'll downclock my intel Q6600 from 2.4GHz to 2.4MHz so it is 1000 times slower and uses 1,000,000 times less energy so it gets a 1000 times better MHash/Joule rating.

[mrb]

If you are just looking for best Mhash/Joule I'll downclock my intel Q6600 from 2.4GHz to 2.4MHz so it is 1000 times slower and uses 1,000,000 times less energy so it gets a 1000 times better MHash/Joule rating.

Except you just increased your cost per Mh/s by a factor 1000x.

This is why GPUs cannot compete with FPGAs even when underclocked/undervolted. Because you still pay full price and end up running the hw at a fraction of the speed it is capable of.

[pieppiep]

So you should add to the question the minimum hashrate for a chip.
But you don't know yet how many chips BFL is using in the new products.

[Cablez]

Shouldn't this be in mining speculation?

I find it tedious that these types of discussion can even continue. There are only 2 probable outcomes: BFL meets their stated specs, which are incomplete or they fail to get what they sold everyone on.

nuff said.

[Glasswalker]

A quick note, it should be confirmed (I haven't the time to read it directly) if this article is talking about MHash/s as in SHA256 Hashes, or MHash/s as in Bitcoin hashes... Remember, a single Bitcoin Hash is 2x SHA256 Hashes... Meaning 1200MHash/s in raw SHA256 Hashes is actually only 600Mhash/s in bitcoin speak.

[mrb]

A quick note, it should be confirmed (I haven't the time to read it directly) if this article is talking about MHash/s as in SHA256 Hashes, or MHash/s as in Bitcoin hashes... Remember, a single Bitcoin Hash is 2x SHA256 Hashes... Meaning 1200MHash/s in raw SHA256 Hashes is actually only 600Mhash/s in bitcoin speak.

Neither. It talks about SHA-256 speed in Gbit/sec. See "Note 1" in my first post.

[mtminer]

Blah, BFL is talking about ~1750MH/Joule Jalapeno, USB device 3.5GH/s @ 2W from USB

And everyone is 100% sure they aren't going to have an external power supply? A small wall wart?

USB 3 is 4.5 W

I think you need to go the other way start at what a US based 20 AMP 120V power plug could supply and work backwards using the 1 THash box.

15 AMPs * 120V == 1800 watts, 80% eff would give 1,440 watts available.

~695MH / Watt

Jalapeno is going to need a wall wart mystery solved?

[Dexter770221]

Blah, BFL is talking about ~1750MH/Joule Jalapeno, USB device 3.5GH/s @ 2W from USB

And everyone is 100% sure they aren't going to have an external power supply? A small wall wart?

USB 3 is 4.5 W

I think you need to go the other way start at what a US based 20 AMP 120V power plug could supply and work backwards using the 1 THash box.

15 AMPs * 120V == 1800 watts, 80% eff would give 1,440 watts available.

~695MH / Watt

Jalapeno is going to need a wall wart mystery solved?

Or Jalapeno will be downclocked and downvolted a little bit to met USB specs. Mystery solved? We may speculate till dawn....
My guess is just like that: Single chip is designed to deliver 4GH/s @ 4W. SC Single will contain 10 of this chips, Mini rig 250. Jalapeno downclocked and downvolted to 3,5GH @ 2,5W.

[rampone]

Y Cable, like some harddrives?

[punin]

Maybe it'll be 3.5Gbit/s per chip?   Maybe they had a "misunderstanding".

[SgtSpike]

Blah, BFL is talking about ~1750MH/Joule Jalapeno, USB device 3.5GH/s @ 2W from USB

And everyone is 100% sure they aren't going to have an external power supply? A small wall wart?

USB 3 is 4.5 W

I think you need to go the other way start at what a US based 20 AMP 120V power plug could supply and work backwards using the 1 THash box.

15 AMPs * 120V == 1800 watts, 80% eff would give 1,440 watts available.

~695MH / Watt

Jalapeno is going to need a wall wart mystery solved?

BFL confirmed (in a thread around here somewhere) that the Jalepeno would run off of the USB port as it's power source, and that it would not require USB 3.0.  Of course, until it actually happens, I'd still call that speculation, but it is at least BFL's goal to have it run only on the USB power alone.

[Coinoisseur]

ITT: People graciously try figuring out how BFL could possibly make good on their ASIC promises by putting them on par with the best MH/J rate and best W/die size rates currently known in the research field (which usually takes 3-10 years to materialize into products if it comes to fruition at all).

[rjk]

ITT: People graciously try figuring out how BFL could possibly make good on their ASIC promises by putting them on par with the best MH/J rate and best W/die size rates currently known in the research field (which usually takes 3-10 years to materialize into products if it comes to fruition at all).

Dude... 65, 45, and even 35 nm are far from experimental. 22nm is current, and we aren't even looking at those numbers, although they would have great performance.

[Coinoisseur]

28nm theoretical Mh/W have been tossed around. Very rosy to think BFL has a VC source willing to pony up 10s of millions up front for that kind of chip development. IMO, given the Bitcoin market 65nm makes the most sense with 45nm, better odds if it's a FPGA->ASIC copy, being an outside possibility.

And the SHA design in OP is definitely experimental/research.

ITT: People graciously try figuring out how BFL could possibly make good on their ASIC promises by putting them on par with the best MH/J rate and best W/die size rates currently known in the research field (which usually takes 3-10 years to materialize into products if it comes to fruition at all).

Dude... 65, 45, and even 35 nm are far from experimental. 22nm is current, and we aren't even looking at those numbers, although they would have great performance.

[rjk]

28nm theoretical Mh/W have been tossed around. Very rosy to think BFL has a VC source willing to pony up 10s of millions up front for that kind of chip development. IMO, given the Bitcoin market 65nm makes the most sense with 45nm, better odds if it's a FPGA->ASIC copy, being an outside possibility.

And the SHA design in OP is definitely experimental/research.

ITT: People graciously try figuring out how BFL could possibly make good on their ASIC promises by putting them on par with the best MH/J rate and best W/die size rates currently known in the research field (which usually takes 3-10 years to materialize into products if it comes to fruition at all).

Dude... 65, 45, and even 35 nm are far from experimental. 22nm is current, and we aren't even looking at those numbers, although they would have great performance.

What I meant was that the processes are mature. As long as you have a good designer, you aren't going to have any issue getting them fabbed. Thus my comment about whether or not it was "experimental".