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Taken from the BFL Facebook (https://www.facebook.com/ButterflyLabs) which linked to Codinginmysleep (http://codinginmysleep.com/first-look-at-bfls-asic-hardware/), here are some renderings of the SC Single:

http://codinginmysleep.com/wp-content/uploads/2012/09/Single_SC_Enclosure-300x234.png

http://codinginmysleep.com/wp-content/uploads/2012/09/BitForce_SC_Front.png

http://codinginmysleep.com/wp-content/uploads/2012/09/BitForce_SC_Back.png

Seems each SC Single will use 8 chips (see them in the center?), which means each one will run at ~5GH/s each. Maybe the Jalapeno is just a downclocked (or lower power) version of a lone chip?

Thanks for the post, We are starved for information!

It would be wery nice to "unlock" japalenos :) Would need additional cooling i guess..

Looks good so far. There are a couple chips hanging off the end and colliding though. lol.

I spy 8 LED's lined up supposedly for each of the ASICs :)

no holes for ventilation on the box ? even with 600MHash/Joule the Single should generate 50Watt of heating.

Better cooling if the chip is suspended in mid air.
Pretty early design, I hope.

Agreed but I bet it gets a fatty heatsink stuck right on those chips.

+1  jalapenos in the fridge

Looks good, sometimes the 3d modeling plugins for circuit board design programs aren't always the best hence the big square capacitors and weird floating chips.

I labeled some stuff if anyone is interested in my spitballing:
http://dl.dropbox.com/u/1181169/ASICsingle.PNG

Ooooh.....Ahhhhh....  ;D

Where's the Flux Capacitor Damnit!?!?!

What good is the blinky little box if I can't line 1.21 Jiggawatts of lightning into it and hash like it was the 80s! :)

40 gh/s  divided by 8 asic chips is 5 gh/s per chip.

so the jally will be crippled to only run at 3.5 gh/s or worse?

BFL has been saying 3.5Ghs from the beginning, this is no surprise. How exactly they plan on doing this is a different tale...

After big chip makers like AMD or Intel manufacture a chip, they run it through production quality control testing.  A chip that is theoretically the same as another chip may exhibit different behaviors under stress.  As a result, some chips in a batch may be binned and sold as 3 Ghz chips.  Other chips in the same batch, that did not perform as well in testing, may be binned and sold as 1.5 Ghz chips.

It is very realistic and following standard commercial practices that the same chips from the same batch might run at slightly different clock speeds, to avoid manufacturing imperfections or whatnot.

So perhaps Jalapeno units are 5 Ghash/sec that did not pass quals at top speed, but do pass quals at lower speeds.

Any sort of scenario like this is possible, standard for chip manufacturing, and not "cheating."

Maybe chips with flaws (they'll always be some in a batch) will be used for the Jally, Just like CPUs are tested then binned to run at certain speeds.

Totally agree. I wasnt implying that they would "cheat" us or anything. more of a serious question as to how they would lower the hash rate. Would it be lowering the clock speed? hardware side? firmware? Possibly software/protocol?

I guess i was really leaning more towards the idea of "Could we 'unlock' the jally and bump it up to 5Ghs? Or 4Ghs?

And the answer is probably predictable (I'm guessing, no inside info): "yes, but you void your warranty, fry your hardware, and have to deal with lockups"

of course if the yeild is so high they use full speed capable chips in the Jally, then those lucky people could up-clock it back to 5Gh/s.

I'm thinking though, rather then down-clock, they might disable hash-cores. (my thinking is the chip will work by having 1000's of individual hashing cores working simultaneosly)

My assumption was 10 chips @ 4GH/s each. In Jally 1 chip downclocked and downvolted just to met USB power specs. I wasn't wrong that much ;)
From my perspective it's oversized and overengeenered. It can be done much more simpler than that.

USB power spec is 1 Watt. To get 3.5GH/s the chip would have to master 3500MH/Joule ... this is possible but unlikely.

2.5W for USB 2.0

Was just going to mention that...

500ma @ 5v = 2.5W

Extrapolating that, if we assume that a 3.5GH/s chip will take up half of the electricity of a 5GH/s chip (power consumption goes up exponentially with speed increase), then a single would use, at max:

2.5W x 2 x 8 = 40 watts.

Interesting...

Consider that a 5850 is a 5870 with one of its 10 shader groups disabled.  A 5830 is the same with 3 groups disabled.  I think they may be clocked lower also.

AMD laser cuts the traces so there is no hope of "unlocking" them.

Aw come on, at least give us the whole deal: http://www.youtube.com/watch?v=4pXfHLUlZf4

BOT: Looks real promising for BFL.

USB is 5V and max current is 0.5A = 2.5W per port.
Dual USB ports = 5 watts.  :)
Laptop CD ROM drives have been doing that trick for years.

Sept 25th... And they show design pics. This would not be allowed on kickstarter.com now days to raise cash.
Ship date.. Hm.. A ways away me thinks. Jan 2013 seems about right.

Even if it is two USB ports 80 watts is still fantastic. 500 Mhash/watt? Yes please.

Well, for me and other BFL customers I hope you're wrong. I did have this thought as well as was going to post the same. One rendering that may have been made a while ago may not be indicative of a delay, as they may have long since moved past that rendering and on to testing of an actual prototype. You make a good point though. With about 45 days left until they're supposed to be delivering product it does make oneself a little concerned if all they've done is just a couple of 3D renders of said product.

Then again, I have no experience in electrical engineering or ASIC design so perhaps this type of emulation and mockup process is the normal procedure.

You'd hope so, if they were going to be delivering in 45 days they'd want to already have moved on to testing prototypes, and at that point we'd probably see inaba's hashrate a lot higher than it is now (they've got to test a prototype mini-rig SC after all).

Hmmmmmmmm

Exactly.  While it isn't absolute proof the lack of photos, benchmarks, pool hashrate at this point makes the deadline seem implausible.  When you look at BFL history and inability to meet deadlines I think January is possible but on the optimistic side.  To be cautious I would leave it at "Q1 2013".

More to the point, I wonder whether BFL will ship before cablepair...

It would make sense if each chip has 4 "cores". One disabled core would give you 3.75 GH/s...

It's more likely that it's clocked slower with a lower voltage. Better power savings that way.

So they only have basic 3d drafts done? Shouldn't they have made these designs way before they even asked for money?

Enough to run off a USB bus, though? Going by BFL's proposed specs, each "full strength" chip would seem to use 10 watts/2.5 amps @5v. Not taking into account other hardware on the board, of course. Not sure you could undervolt/clock it enough. So either it will have to run off more than USB power, or it's a completely different chip.

Well, to give them the benefit of the doubt, kind of hard to finalize any hardware when you don't have any production chips to test your design with.

They asked for money because they didn't or still don't have enough "capital venture" funds to produce and fully develop the ASICs.

If not enough people pre order then no ASIC for you.

There are several steps involved in the type of project that BFL is doing.  Here's a general overview of the procedure they might be following.  We do this where I work, but in general, we don't do step #1 because we use off the shelf parts in most products.

If you need money to complete the steps, I guess you have to ask for it up front ;D.

1a) ASIC (or whatever they are using) design:

The engineers will define the interfaces of the ASIC (power, digital and analog interfaces), and also decide at a high level how the guts of the chip will be put together (think block diagram).

1b)Implementation:

During this step, the designers work on implement the guts of the hashing chip and laying it out in the chip based on step 1.

1c)ASIC manufacture:

At this point, BFL will know how to use their ASIC (what the pinouts are and how to talk to the chip).  All that is left is for the fab to actually make the chip.  The fab or other company may also test the chip based on test vectors provided by BFL.  BFL may also do this in house on the final PCB or a test PCB.

2) Schematic capture / system design - deciding which other electronic components in addition to the ASICs are required, and hooking them all together.  This step can be started even before step 1 is complete.  Once step 1a is complete, the ASICs can be hooked up once the final pinouts and communication/power requirements are known, completing step 2.

3) Mechanical design:

How big can the PCB be?  Where do we place the parts on the PCB to make them fit?  How much clearance do you have?  How much heat has to be dissipated (airflow/heatsink requirements)?  This step would normally happen in parallel with #2.

The picture in the OP is the result of #3 with input from #2 and #4 (because the PCB routing can change where parts are placed).  However, the picture does not actually mean that step 4 is complete.  However, It might be finished because there is top/bottom layer routing that is visible.  Based on their proposed release date, either they have the boards already or are just waiting for them to arrive.

4) PCB part placement and routing:

Based on the data gathered from #3, the electrical design team must actually place the required parts determined in step 2.  Once the parts are placed on the PCB, the actual components must be connected as per step 2.  The parts are connected via traces on multiple layers on the PCB.  During this step, parts may also be moved around to make the routing easier.

5) PCB manufacturing and assembly:

A company manufactures the PCB and then places and solders the req5ired components onto the board.

6) Turn on and test

Now it's time for BFL to get the board, and figure out what actually happens when they turn on the power...  Errors that were not caught during the previous ste6s may be correctable with mods.

7) Done??

If all goes well, the product is finished!  Any problems that could not be corrected by mods will require you to create a new version of the board or ASIC.

Does this mean if the ASIC chips become obsolete, then the PCB can be reused for another ASIC chip to do another task (or the same task but better) ?
If so then this could potentially create a trade in value again.

The chips in the rendering are soldered on, so no.

Yes I see, I didn't mean you can replace it like a socketed chip, I meant it could be sent off to a special machine that removes the chips, re-balls and solders new ones on, laptop manufactures do this with failed integrated GPUs on laptop motherboards.

Sounds more expensive to do than buy a new pcb.

Mark my words. This is a scam.

I don't believe anybody that says anything here. You are all crazy.

It would be if there were many different PCBs, but because they are all the same, it only takes a one time setting up of the machine, and after that the process is automated.
Ofcourse it all depends on how much the PCB costs.

Diode ?? uses <part #>
Diode ?? uses <part #>
SMD ???? jack ?? uses <part #>
Switching regulator ?? uses <part #>
For 2.2uH inductor use <part #>

Are you a GPU miner about to lose your investment?

/ontopic
I understand the CPU clocking explanations given, but isn't the manufacturing process something that yields predictable results? Ok, let's say there are some rejection rates of ... 1%?

I was expecting the jala to be a full working ASIC chip, the Single to be X working chips and so on. The difference in price between them would be from:
(++) additional materials used (i.e. fan, more electronic components, more metal in the case)
(--) discount from buying "chips in bulk".

Not from dwarfing a chip down.

It depends on if BFL plans on using semi-defective chips with a crippled pipeline or simply reduced clockspeed. It's entirely possible that the Jalapenos may be using full speed capable ICs but we won't really know until someone gets their hands on one and wants to risk damaging it to probe around the board and figure out what BFL has done.

Why does it matter?

Doesn't matter that much but it helps managing expectations and perceptions/perceived value. Something BFL could use some more :)

I still don't see why...  as long as the chips meet the stated specs (gimp-binned or not), buyers should be satisfied.

What is the practical difference between a "full working ASIC" chip and "dwarfing a chip down" if they both mine at 3.5 GH/s?  Why do you care?

One can be OC'd to the full 5GH/s for a single chip. The other cannot.  ;D ;D ;D

That is fine with the smileys and all...  as long as you realize these expectations are unrealistic and far beyond what major chipmakers like AMD and Intel guarantee.

Yes, I'm well aware that this is almost certainly not possible.  ;)

Running 8x of the chips at full speed (5Gh/s) and voltage in the SC Single then under-volting and under-clocking 1x of the chips in the Jalapeno makes perfect sense from a thermal (heat) perspective.  I think the Single will have a large heatsink and fan similar to the current FPGA Singles while the Jalapeno will have a tiny heatsink and no fan.  It's all about the heat and how to get rid of it. 

This is also a good strategy for yield improvement.  Why do you think Intel, AMD and nVidia have different speed bins for their chips?  They would love to have all of their chips run at 4GHz or (much) higher but this is not how chip production works.  Instead, there is a distribution curve of varying speeds in any given "lot" (or batch) of chips.  Some are faster than average, others are slower.  The Jalapeno allows BFL to sell chips that are fully functional but not quite fast enough for the SC Single or SC mini-rig performance points.  (If anyone asks I can elaborate on this further.)

Marketing and price / performance points are also a factor I assume.  (For example, why have a $149 price point at all?  The current "low end" of the BFL product line it roughly 4x that.  Why not keep the cheapest price in the $500 to $600 range?  A: Marketing.)

Remember, the Jalapeno only needs to dissipate ~5W of heat. Not a lot of heat to even worry about getting rid of.

Nothing incredibly valuable here, but it's relatively interesting:

CMS05 Schottky Diode (could be a CMS03)
http://www.digikey.com/product-detail/en/CMS05(TE12L,Q,M)/CMS05QMCT-ND/871536

SS3P4 Schottky Diode
http://www.digikey.com/product-detail/en/SS3P4L-M3%2F86A/SS3P4L-M3%2F86AGITR-ND/2048204

PJ-003B-SMT
http://www.digikey.com/product-detail/en/PJ-003B/CP-003B-ND/96972

ST1S30 Buck Regulator
http://www.digikey.com/product-detail/en/ST1S30IPUR/497-11048-1-ND/2571073

2.2uH Inductor something like: IHLP3232DZER3R3M01 (specific is not that important)
http://www.digikey.com/product-detail/en/IHLP3232DZER3R3M01/541-1373-2-ND/2657469

No, I'm not a miner. But I know a scam when I see one. And this is a scam. S.C.A.M.

Crazyates,

Fix the god-damned title. It's pissing me off now.

Fix it to what? I just quoted it to the title of the article the pictures came from.

*Folds arms*
*Raises eyebrow*
*Taps foot*
...

I thought about that too and it makes sense. Perhaps a "full" peno would have gotten a little too hot and would have required a fan? To keep the low-end device simple(r), they decided to underclock it.

*smacks P_shep*

FRIST, man

FRIST

How that gets passed anyone is beyond me.

 :D

I didnt notice it either....

neat

Perhaps you meant PAST instead of PASSED???   ;D  (Live in a glass house very long???)

Pretty sure 'passed' is correct.

My bad. I make those kinds of mistakes all the time.

Pretty sure it's not.

Yes, it is a word.
No, it is not the right word in this context.

Much better :)

Really?

http://dictionary.reference.com/browse/past?s=t (http://dictionary.reference.com/browse/past?s=t)
adverb
13.
so as to pass by or beyond; by: The troops marched past.


http://dictionary.reference.com/browse/passed?s=t (http://dictionary.reference.com/browse/passed?s=t)

So much speculation. If this... Maybe that... I might...

Come on guys, keep those imaginations in check, greed ≠ logic.

Don't be.  It was a joke.  It is 'past'.

Mistakes like that never get passed me.

I passed something, but it wasn't a mistake.

it was your dignity.

Close... it was a nice fat CJ on the throne.

Looks like somebody got a booboo, im sorry did i hurt you?  :P

The day you are more than a foot note on my toilet paper is the day I stop reading Bitcoin Talk.

Some ego, i guess i will never reach your stature... as a talking piece for a massive walking scam.

You're right, it's hard to reach my stature living in your mom's basement, eating Cheetos.  Good luck, though.

PS - If you want your balls to stop turning orange, stop eating Cheetos.

Says the etard that spends his life replaying to posts on a forum.

PS - And has time to edit them too...

That is almost sig worthy!  ;D

Wow... worked hard on that, did you?

Well somebody ate their wheaties today, done playing ethug?

Is this Dragonball Z?  ???

Are we going to see watercooled ASICs?

Do you mind NOT posting ON TOPIC replies, please?

Sheesh, some people.

I passed some gas

edit: this wasn't the topic?

I would love to see the SEC debrief on this, some intern is explaining it to the rest of the room with a report he passed around.

Intern:
"Yes sir, here are the specs they are advertising"
Boss:
"What about a photo of the product?"
Intern:
"Page 3 sir, its the black box looking gizmo."
Boss:
"Its stated that the image source is verified, where was it located?"
Intern:
"Facebook."
Boss:
"............."

"Your a fucking idiot."

I'm trying to work on that, need mechanical drawings

You are wrong, and you don't have enough self-confidence to put your money where your mouth is by betting against BFL here: http://betsofbitco.in/item?id=665

Why doesn't this board have pads for decoupling capacitors for the ICs? Usually they are placed on the bottom of each chip!

Here's a raspberry pi bottom.
http://i.i.com.com/cnwk.1d/i/tim/2012/06/19/Raspberry_Pi_35332544_04_1.jpg

Very interesting. It looks like they have two power phases, each with 6 ST1S30s. The ST1S30 is rated for 3A, so assuming all 12 were running at full output current you'd have 36A or so of whatever the rail voltage is, commonly 1.2V.

It's also interesting if they actually are using ST1S30, since it has an absolute maximum rating of 7V and the common input voltage is 5V. I wonder if they're bringing 5V in through the barrel jack, or if one of the other chips is meant to convert 12V->5V. If there was, I'd guess it would be the one at the top left that looks a little floating off in space in the render, but without knowing what actual part they used it would be hard to tell if it's capable of outputting 10A.

It greatly speeds production and reduces cost if you can run components on a single layer. Again it's hard to tell from the renders because the schematic capture and layout software often does goofy stuff with a 3D model (especially if BFL is using their own part libraries), but it kind of looks like the ASICs are packaged in QFNs as opposed to BGAs. If that's the case you'd actually want the decoupling on the top layer, and you can see some of them around the ICs.

Here;s the Deep crack ASIC board. Each Deepcrack chip (qfp) has clearly visible decoupling caps.

http://upload.wikimedia.org/wikipedia/commons/b/bd/Board300.jpg (http://upload.wikimedia.org/wikipedia/commons/b/bd/Board300.jpg)

http://upload.wikimedia.org/wikipedia/commons/6/61/Chip300.jpg

I think so, but instead of waiting really long to fight and have arguments and grunts beforehand, we wait really long for either side to show reasonable evidence and we argue and grunt beforehand.

Now look at that.

For those who don't follow the SA thread on the Bitcoin Drama: Look closely at this rendering. There are some chips sticking over the board and also some chips are overlapping. (on the right for those who can't see it)
Also I noticed that the mounting holes in the middle are too close to the traces from the pins of the middle chips.



Marked.
The fallout from this will be epic.  :D

You're really hung up on these decoupling capacitors, aren't you. lol

Looking at their layout, it looks like they're doing the right thing by secluding the power domains of the ASICs from other dirty power. And they're probably using the inter-layer capacitance to their advantage against noise (probably at least a 6-layer board?). The larger IC-looking devices around the outside of the ASICs look to be capacitors (according to their silkscreen designators).

They have a few caps in the middle of the ASIC array and a few in between them. I would be rather surprised if they placed decoupling caps underneath the ASICs as you mentioned. It looks like they're trying to sink a lot of heat through the bottom, note the large vias on the bottom underneath each ASIC. My guess is they will make those vias un-tented and place a heat sink(s) on the bottom to extract that heat.

Again, that doesn't necessarily mean anything that the 3D render doesn't look correct. They often don't, depending on the package you use and how much time was put into the component models. Take a look at some of those ceramic caps like the one before U4 and U8, they're unrealistically high. That doesn't mean the actual component will be that high. There's issues with the 3D render, but not enough that I'd call it a fake. Maybe you could convince them to release the gerber of the top copper layer. It wouldn't be enough for a competitor to get any real information from, but it would give those of us who are curious a little more information.

I mistyped the overlapping chips on the layout is actually on the left, also some on the bottom.

Anyway, right of course this isn't proof of fraudulent activity. A simple explanation could be that it was just a quick job without particular attention to detail. I'm not one of these people who are convinced of a scam, although given the recent background check and the whole confidence game taking place I consider it a strong possibility.

It is simply that given the track record of bitcoin there is a certain feeling to legitimate enterprises here. Something about openness and community involvement which simply aren't present with BFL. Look at the X6500 or ZTEX as an example, then look at Mybitcoin and Bruce Wagner.
It's a certain feeling of professionalism which comes with legitimacy. Again this is not generally true but only a strong indicator.
Make up your own mind.  :)

But...but...that requires rational thought   :(

 :)

Yeah I pointed out earlier that often when using stock PCB rendering models they often do not do a very good job of conveying what the actual boards would look like. I do not see any glaring faults in the design.

Now if look you closely at this post, just can see it's pretty obvious that the poster has absolutely no idea what they are talking about. Of course this isn't proof of total ignorance. A simple explanation is that it was a quick trolling without particular attention to detail. I'm not one of these people who are convinced of blanket trolling, although given the recent trolling posts and the whole trolling game taking place I consider it a strong possibility.

Hate to quote myself but...
I love how you weren't able to make fun of this part.  ::)

I actually enjoy a bit of electric mucus...but that right there is funny as fuck