First Look at BFL's ASIC Hardware

[crazyates]

Taken from the BFL Facebook which linked to Codinginmysleep, here are some renderings of the SC Single:







Seems each SC Single will use 8 chips (see them in the center?), which means each one will run at ~5GH/s each. Maybe the Jalapeno is just a downclocked (or lower power) version of a lone chip?

[squall1066]

Thanks for the post, We are starved for information!

[monstrs]

It would be wery nice to "unlock" japalenos Would need additional cooling i guess..

[abeaulieu]

Looks good so far. There are a couple chips hanging off the end and colliding though. lol.

I spy 8 LED's lined up supposedly for each of the ASICs

[tytus]

no holes for ventilation on the box ? even with 600MHash/Joule the Single should generate 50Watt of heating.

[psilan]

Looks good so far. There are a couple chips hanging off the end and colliding though.

Better cooling if the chip is suspended in mid air.
Pretty early design, I hope.

[tgmarks]

Agreed but I bet it gets a fatty heatsink stuck right on those chips.

[SLok]

It would be wery nice to "unlock" japalenos Would need additional cooling i guess..

+1  jalapenos in the fridge

[Photon939]

Looks good, sometimes the 3d modeling plugins for circuit board design programs aren't always the best hence the big square capacitors and weird floating chips.

I labeled some stuff if anyone is interested in my spitballing:

[Nolo]

Ooooh.....Ahhhhh.... 

[Glasswalker]

Where's the Flux Capacitor Damnit!?!?!

What good is the blinky little box if I can't line 1.21 Jiggawatts of lightning into it and hash like it was the 80s!

[fcmatt]

40 gh/s  divided by 8 asic chips is 5 gh/s per chip.

so the jally will be crippled to only run at 3.5 gh/s or worse?

[AmDD]

40 gh/s  divided by 8 asic chips is 5 gh/s per chip.

so the jally will be crippled to only run at 3.5 gh/s or worse?

BFL has been saying 3.5Ghs from the beginning, this is no surprise. How exactly they plan on doing this is a different tale...

[jgarzik]

40 gh/s  divided by 8 asic chips is 5 gh/s per chip.

so the jally will be crippled to only run at 3.5 gh/s or worse?

BFL has been saying 3.5Ghs from the beginning, this is no surprise. How exactly they plan on doing this is a different tale...

After big chip makers like AMD or Intel manufacture a chip, they run it through production quality control testing.  A chip that is theoretically the same as another chip may exhibit different behaviors under stress.  As a result, some chips in a batch may be binned and sold as 3 Ghz chips.  Other chips in the same batch, that did not perform as well in testing, may be binned and sold as 1.5 Ghz chips.

It is very realistic and following standard commercial practices that the same chips from the same batch might run at slightly different clock speeds, to avoid manufacturing imperfections or whatnot.

So perhaps Jalapeno units are 5 Ghash/sec that did not pass quals at top speed, but do pass quals at lower speeds.

Any sort of scenario like this is possible, standard for chip manufacturing, and not "cheating."

[P_Shep]

Maybe chips with flaws (they'll always be some in a batch) will be used for the Jally, Just like CPUs are tested then binned to run at certain speeds.

[AmDD]

Totally agree. I wasnt implying that they would "cheat" us or anything. more of a serious question as to how they would lower the hash rate. Would it be lowering the clock speed? hardware side? firmware? Possibly software/protocol?

I guess i was really leaning more towards the idea of "Could we 'unlock' the jally and bump it up to 5Ghs? Or 4Ghs?

[jgarzik]

I guess i was really leaning more towards the idea of "Could we 'unlock' the jally and bump it up to 5Ghs? Or 4Ghs?

And the answer is probably predictable (I'm guessing, no inside info): "yes, but you void your warranty, fry your hardware, and have to deal with lockups"

[P_Shep]

of course if the yeild is so high they use full speed capable chips in the Jally, then those lucky people could up-clock it back to 5Gh/s.

I'm thinking though, rather then down-clock, they might disable hash-cores. (my thinking is the chip will work by having 1000's of individual hashing cores working simultaneosly)

[Dexter770221]

My assumption was 10 chips @ 4GH/s each. In Jally 1 chip downclocked and downvolted just to met USB power specs. I wasn't wrong that much
From my perspective it's oversized and overengeenered. It can be done much more simpler than that.

[tytus]

USB power spec is 1 Watt. To get 3.5GH/s the chip would have to master 3500MH/Joule ... this is possible but unlikely.