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Author Topic: First Look at BFL's ASIC Hardware  (Read 16054 times)
P_Shep
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September 25, 2012, 10:42:50 PM
 #21

USB power spec is 1 Watt. To get 3.5GH/s the chip would have to master 3500MH/Joule ... this is possible but unlikely.

2.5W for USB 2.0
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September 25, 2012, 10:53:09 PM
 #22

USB power spec is 1 Watt. To get 3.5GH/s the chip would have to master 3500MH/Joule ... this is possible but unlikely.

2.5W for USB 2.0
Was just going to mention that...

500ma @ 5v = 2.5W

Extrapolating that, if we assume that a 3.5GH/s chip will take up half of the electricity of a 5GH/s chip (power consumption goes up exponentially with speed increase), then a single would use, at max:

2.5W x 2 x 8 = 40 watts.

Interesting...
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September 25, 2012, 11:53:21 PM
 #23

of course if the yeild is so high they use full speed capable chips in the Jally, then those lucky people could up-clock it back to 5Gh/s.

I'm thinking though, rather then down-clock, they might disable hash-cores. (my thinking is the chip will work by having 1000's of individual hashing cores working simultaneosly)

Consider that a 5850 is a 5870 with one of its 10 shader groups disabled.  A 5830 is the same with 3 groups disabled.  I think they may be clocked lower also.

AMD laser cuts the traces so there is no hope of "unlocking" them.

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September 26, 2012, 12:25:12 AM
 #24


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September 26, 2012, 12:56:56 AM
 #25

Aw come on, at least give us the whole deal: http://www.youtube.com/watch?v=4pXfHLUlZf4

BOT: Looks real promising for BFL.

Tired of substandard power distribution in your ASIC setup???   Chris' Custom Cablez will get you sorted out right!  No job too hard so PM me for a quote
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September 26, 2012, 01:31:02 AM
 #26

USB power spec is 1 Watt. To get 3.5GH/s the chip would have to master 3500MH/Joule ... this is possible but unlikely.

USB is 5V and max current is 0.5A = 2.5W per port.
Dual USB ports = 5 watts.  Smiley
Laptop CD ROM drives have been doing that trick for years.
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September 26, 2012, 01:49:22 AM
 #27

Sept 25th... And they show design pics. This would not be allowed on kickstarter.com now days to raise cash.
Ship date.. Hm.. A ways away me thinks. Jan 2013 seems about right.
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September 26, 2012, 01:51:39 AM
 #28

USB power spec is 1 Watt. To get 3.5GH/s the chip would have to master 3500MH/Joule ... this is possible but unlikely.

USB is 5V and max current is 0.5A = 2.5W per port.
Dual USB ports = 5 watts.  Smiley
Laptop CD ROM drives have been doing that trick for years.

Even if it is two USB ports 80 watts is still fantastic. 500 Mhash/watt? Yes please.

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September 26, 2012, 01:56:41 AM
 #29

Sept 25th... And they show design pics. This would not be allowed on kickstarter.com now days to raise cash.
Ship date.. Hm.. A ways away me thinks. Jan 2013 seems about right.

Well, for me and other BFL customers I hope you're wrong. I did have this thought as well as was going to post the same. One rendering that may have been made a while ago may not be indicative of a delay, as they may have long since moved past that rendering and on to testing of an actual prototype. You make a good point though. With about 45 days left until they're supposed to be delivering product it does make oneself a little concerned if all they've done is just a couple of 3D renders of said product.

Then again, I have no experience in electrical engineering or ASIC design so perhaps this type of emulation and mockup process is the normal procedure.

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September 26, 2012, 02:14:37 AM
 #30

Sept 25th... And they show design pics. This would not be allowed on kickstarter.com now days to raise cash.
Ship date.. Hm.. A ways away me thinks. Jan 2013 seems about right.

Well, for me and other BFL customers I hope you're wrong. I did have this thought as well as was going to post the same. One rendering that may have been made a while ago may not be indicative of a delay, as they may have long since moved past that rendering and on to testing of an actual prototype. You make a good point though. With about 45 days left until they're supposed to be delivering product it does make oneself a little concerned if all they've done is just a couple of 3D renders of said product.

Then again, I have no experience in electrical engineering or ASIC design so perhaps this type of emulation and mockup process is the normal procedure.
You'd hope so, if they were going to be delivering in 45 days they'd want to already have moved on to testing prototypes, and at that point we'd probably see inaba's hashrate a lot higher than it is now (they've got to test a prototype mini-rig SC after all).
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September 26, 2012, 02:18:58 AM
 #31

Hmmmmmmmm

This is not some pseudoeconomic post-modern Libertarian cult, it's an un-led, crowd-sourced mega startup organized around mutual self-interest where problems, whether of the theoretical or purely practical variety, are treated as temporary and, ultimately, solvable.
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September 26, 2012, 02:20:49 AM
 #32

Exactly.  While it isn't absolute proof the lack of photos, benchmarks, pool hashrate at this point makes the deadline seem implausible.  When you look at BFL history and inability to meet deadlines I think January is possible but on the optimistic side.  To be cautious I would leave it at "Q1 2013".
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September 26, 2012, 02:22:46 AM
 #33

Exactly.  While it isn't absolute proof the lack of photos, benchmarks, pool hashrate at this point makes the deadline seem implausible.  When you look at BFL history and inability to meet deadlines I think January is possible but on the optimistic side.  To be cautious I would leave it at "Q1 2013".
More to the point, I wonder whether BFL will ship before cablepair...
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September 26, 2012, 02:40:05 AM
 #34

Maybe chips with flaws (they'll always be some in a batch) will be used for the Jally, Just like CPUs are tested then binned to run at certain speeds.

It would make sense if each chip has 4 "cores". One disabled core would give you 3.75 GH/s...
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September 26, 2012, 03:18:56 AM
 #35

Maybe chips with flaws (they'll always be some in a batch) will be used for the Jally, Just like CPUs are tested then binned to run at certain speeds.
It would make sense if each chip has 4 "cores". One disabled core would give you 3.75 GH/s...
It's more likely that it's clocked slower with a lower voltage. Better power savings that way.

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September 26, 2012, 03:27:53 AM
 #36

So they only have basic 3d drafts done? Shouldn't they have made these designs way before they even asked for money?

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September 26, 2012, 03:29:57 AM
 #37

Maybe chips with flaws (they'll always be some in a batch) will be used for the Jally, Just like CPUs are tested then binned to run at certain speeds.
It would make sense if each chip has 4 "cores". One disabled core would give you 3.75 GH/s...
It's more likely that it's clocked slower with a lower voltage. Better power savings that way.

Enough to run off a USB bus, though? Going by BFL's proposed specs, each "full strength" chip would seem to use 10 watts/2.5 amps @5v. Not taking into account other hardware on the board, of course. Not sure you could undervolt/clock it enough. So either it will have to run off more than USB power, or it's a completely different chip.
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September 26, 2012, 03:31:01 AM
 #38

So they only have basic 3d drafts done? Shouldn't they have made these designs way before they even asked for money?

Well, to give them the benefit of the doubt, kind of hard to finalize any hardware when you don't have any production chips to test your design with.
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September 26, 2012, 03:33:45 AM
 #39

So they only have basic 3d drafts done? Shouldn't they have made these designs way before they even asked for money?

They asked for money because they didn't or still don't have enough "capital venture" funds to produce and fully develop the ASICs.

If not enough people pre order then no ASIC for you.

                   
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September 26, 2012, 05:05:36 AM
 #40

So they only have basic 3d drafts done? Shouldn't they have made these designs way before they even asked for money?

There are several steps involved in the type of project that BFL is doing.  Here's a general overview of the procedure they might be following.  We do this where I work, but in general, we don't do step #1 because we use off the shelf parts in most products.

If you need money to complete the steps, I guess you have to ask for it up front Grin.

1a) ASIC (or whatever they are using) design:

The engineers will define the interfaces of the ASIC (power, digital and analog interfaces), and also decide at a high level how the guts of the chip will be put together (think block diagram).

1b)Implementation:

During this step, the designers work on implement the guts of the hashing chip and laying it out in the chip based on step 1.

1c)ASIC manufacture:

At this point, BFL will know how to use their ASIC (what the pinouts are and how to talk to the chip).  All that is left is for the fab to actually make the chip.  The fab or other company may also test the chip based on test vectors provided by BFL.  BFL may also do this in house on the final PCB or a test PCB.

2) Schematic capture / system design - deciding which other electronic components in addition to the ASICs are required, and hooking them all together.  This step can be started even before step 1 is complete.  Once step 1a is complete, the ASICs can be hooked up once the final pinouts and communication/power requirements are known, completing step 2.

3) Mechanical design:

How big can the PCB be?  Where do we place the parts on the PCB to make them fit?  How much clearance do you have?  How much heat has to be dissipated (airflow/heatsink requirements)?  This step would normally happen in parallel with #2.

The picture in the OP is the result of #3 with input from #2 and #4 (because the PCB routing can change where parts are placed).  However, the picture does not actually mean that step 4 is complete.  However, It might be finished because there is top/bottom layer routing that is visible.  Based on their proposed release date, either they have the boards already or are just waiting for them to arrive.

4) PCB part placement and routing:

Based on the data gathered from #3, the electrical design team must actually place the required parts determined in step 2.  Once the parts are placed on the PCB, the actual components must be connected as per step 2.  The parts are connected via traces on multiple layers on the PCB.  During this step, parts may also be moved around to make the routing easier.

5) PCB manufacturing and assembly:

A company manufactures the PCB and then places and solders the req5ired components onto the board.

6) Turn on and test

Now it's time for BFL to get the board, and figure out what actually happens when they turn on the power...  Errors that were not caught during the previous ste6s may be correctable with mods.

7) Done??

If all goes well, the product is finished!  Any problems that could not be corrected by mods will require you to create a new version of the board or ASIC.
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