ASICMiner sells those little 300MH/s USB devices, as well as those 10GH/s Blades, but both are WAY overpriced. Like nasty outright price gorging.
But quite profitable if you just put them straight on ebay and sell to some gullible punters. Of course that can't go on for ever, but easy money for now. As for the moral aspect? |
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230gh/s plus some more whwn cooler  bren on gild for a week tomorrow and it sayd in my stats I found 2 blocks.... so thought I would try for a week or so while I still stand a chancr Thanks for the quick reply, I'd only just found the answer in your post history (hence my edit above). Reminder to self: always check posters history before firing off a quick reply  But yes, I am interested in whether you need any specific configuration to reduce the orphan rate. Anyone know? |
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Thank you sam! Will try this later on hopfully I can report back with finding a block witjin the nexy week So how many 100GH/s are you running then?OK, I found this in your post history ... producing around 230GH/s just now on btcguild
I'd be interested in how many of your found blocks are orphaned as I understand that solo mining requires careful configuration of your peers to maximise your network connectivity. |
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A street preacher with 18 posts ... how much credibility can he gets and out of the blue he comes here preaching, he probably would do the same last year before avalon launched their asic miner.
Ad hom. Play the ball, not the man  |
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But they are entering a whole new ballgame: shipping complete retail products.
Designing the core is one thing, turning it into a product and managing the whole pipeline is quite another. These are two completely different businesses.
They have a company making them, they have a company assembling them, what makes you think they don't have a company shipping them too? What's more, they will be shipping prototypes. They don't even have a chip test strategy in place yet! It will be several months after first silicon that they will be in a position to ship production quality goods. But in this respect they are in exactly the same boat as Avalon and BFL. Welcome to the bleeding edge of electronics design |
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And speaking of said, here are some questions you shouldask anyone wanting your money up front for any asic product:
1. Who is the silicon foundry?
2. Are you using a Multi Project Wafer service or a full mask set?
3. What is the chip size?
4. How many pipelines does it have and what is the operating frequency?
5. What is the target package type?
6. If you are using a full mask set ($1.6 - $2.3 Million for 28nm) who or how are you financing it and what are your contingency plans if you need a respin?
7. To get '90 day' production you need a lot of chips, meaning you need several wafers (costing 15 - 30k dollars each in a small geometry). Refer to 6 above.
8. What software tools have you used for development and if they are commercial ones like Cadence, exactly how have you financed them up to now?
9. What happens to my money/order if you miss the 90 day target?
10. Will you publish an order backlog summary for purchasers to examine?
11. Will you publish the invoice for NRE for purchasers to see? (ie to see that it really is x nm)
Feel free to add your own. There is absolutely no reason for any company wanting your money NOT to answer these questions.
There has been 2 open days at KNCminer. They answered pretty much all the questions asked to them. You could have sendt your questions with someone attending. Wow, the fanboi's have certainly been to town on this one. I'm going to side with brontosaurus as his questions 1 thru 8 are very pertinent. As for the open day, from BitcoinOrama's report https://bitcointalk.org/index.php?topic=232852.0 the most telling fact that was disclosed was that KNCMiner's ASIC has a huge die size and they have absolutely no wafer or packaged device test strategy. They are just going to solder the chips on boards and hope for the best. There will be tears  |
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Awesome blog post! Can you comment on how many chips in total you received? I count aprox 190 chips from your picture, can you verify? Looking forward to the test results. Good luck!
Picture of packaging says 217, tray looks to have 240 slots, though how it came out of that package I cannot say (maybe it folds in half?) Minor quibble about lack of anti-static handling, but they're prototypes so whatever (and its pretty humid in HK). PS What MSL are these QFN packages? May not be a good idea to get them too damp. |
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But its been hinted that KNCMiner are doing a 28nM Structured ASIC, ie a HardCopy(tm) of an Altera FPGA design. That's much cheaper in up-front cost (the mask set is just the metalization/vias so much cheaper), but the per-unit cost is higher. It won't perform anything like a full custom ASIC. https://bitcointalk.org/index.php?topic=228068.msg2433194#msg2433194 (and subsequent posts). My concern is that they're making very lofty performance claims but if it's just an ASIC copy of the FPGA it's not likely to outperform the FPGA crazy significantly. I'm not sure where they're getting all this extra performance per watt from, are they solely depending on the fact that it's 28nm? I'm just worried it'll be another repeat of BFL's power estimates. They might be able to get 350Ghash but I doubt it's going to be come at the low watts they're quoting. I'm not sure I understand your meaning. ASICs are much faster and more efficient than FPGAs. Nothing they've claimed is outside the realm of reality for a non-structured ASIC such as they claim to be using. It's just a real ASIC. I agree. A Structured ASIC whould have little performance gain over the base FPGA part (its essentially the same device, but with the programming hard-wired in), but would have lower unit cost. A full custom ASIC is an entirely different beastie, and at 28nm would expect at least a factor of 2 performance gain over BFL (not quite sure how it scales, ChipGeek will know). I feel rather sorry I brought up this Structured ASIC hypothesis now as its pretty clear from KNCMiner statements that this is wrong (though I was only quoting what had been said elsewhere). I do stand by my comments that their timescale is extremely ambitious and the lack of a test strategy at wafer/package level is very worrying. (And my thanks to ChipGeek for his comments above.) |
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Believers.... believers..... let us pray for the skeptics.... thy miners will be done.
That image is just way too big. Have a thought for us poor souls browsing on a Raspberry Pi |
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Awful lot of money to get "free" electricity, considering how little a Pi uses in the first place.
Agreed, these solar powered mining threads are rather insane, but he did ask a good question (how to do solar UPS el cheapo). BTW What is it with all these strange HOW-TO-DO-XXX threads recently? Someone opened up a competition or what? |
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Thanks for the advice, I think I may give it a shot.
Just be careful not to overvolt your mining rig (slightly undervolting the 12V supply will probably be OK), you'll want a multimeter to check the voltages, and also the currents from the mains and solar supplies to ensure you've balanced them OK. |
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Is there any security risks in sending a rawtx to a third party, eg exposing addresses etc? Obviously the entire network would see it at some point..
The only risk is that they don't forward it onto the network. There is nothing in the rawtx that is not already in the blockchain. |
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I'd also be interested if there is a simple solution to make up any deficit from the grid without grid tie.
Something as simple as a couple of blocking diodes should do the trick (ideally high current schottky to reduce the voltage drop). Run a 12V mains PSU (always on, so make sure its an efficient one with low quiescent draw), blocking diode to prevent reverse-feed, and run in parallel with the solar panel (use another blocking diode). Panel will supply power when the sun is up, mains when its down. Make sure you include fuses and size your cables appropriately. The PRO's would use an auto-switching UPS, but you asked for simple. PS Probably not such a good idea to use this as a raw 12 volt supply to your kit as a 12 volt solar panel can output up to 18 volts in full sun under no load. You will need some power conditioning to regulate this down (eg the charge controller described in the OP unless you are really into DIY electronics and want to homebrew a regulator). |
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Hi,
I've heard from some people that you can make your own FPGAs even without buying Spartan or whatever development kits. My question is: can you really do it? If so, how? (links to guides appreciated) I really like Bitcoin in general and want to mine a bit better than with my GPUs.
And maybe a little extra question - is it worth?
See https://bitcointalk.org/index.php?topic=9047.0Good fun (if you are into that sort of thing), but no longer profitable to mine on development boards (unless you've already got one lying around at unused home/work/school, but don't buy one just for mining). |
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Titter.
But, lulz aside, too many scams these days, newbies no know any shit. U playing dangerous.
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But ORSoC have a strong relationship with both foundries, it's not like they are selecting people they haven't worked with. They are negotiating delivery for Sept.
Yeah, good point. My experience was with new entrants with wide-eyed expectations. I'm still rather worried about the lack of a test strategy. But in my day yields of 30-60% were common, if they can manage 95% today, them maybe the build it and pray approach will work (it certainly seems to be what BFL used). Read the artice I linked. It shows the sort of timescales the professionals work to. |
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There are two competing foundries, we were told who they were, both have the final design, both are bidding for the gig. Sam mentioned something of huge interest here in front of us. So i'm not the only one who heard this, but I'm not sure I can repeat it; so I won't, but it involves meeting the September deadline.
Yes, but the point I am making is that this s very late in the game to be selecting your foundry. OK, there has been a lot of progress since I left the industry 20 years back, but this is a very tight schecdule. Perhaps I should quote again the article linked by KS in the other thread http://www.edn.com/design/systems-design/4319891/The-economics-of-structured-and-standard-cell-ASIC-designs (2006 vintage but still relevant). I wish some of the current ASIC design gurus would comment on this (several very informed guys post on these threads). |
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Granted... at least voltage tests and i/o tests seem simple enough... but on the other hand, if they're capable of excluding defective engines through an automated process onboard - then there's really little reason to pre-test anything.
Well, there is the matter of an expensive test socket/interface to be designed and procured. And did you note they have not even selected their foundry yet. In another post I noted the over-optimism of ASIC customers (ie KNCMiner in this context, as the customer of the foundry), that was 20 years ago. Seems nothing has changed. There will be tears. PS I edited for clarity, hence the difference from firefop's quote below. |
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I'll repeat this here ... My takeaway from that ...
There is no wafer test.
There is no packaged chip test.
They are simply going to solder the chips on the boards and hope any defects are not fatal (ie unusable boards).
Their yield had better be pretty good for that strategy to work.
(Disclosure, my first job in ASIC industry: test engineer, though things may well have come on a bit in the last 30 years). (Ignore, argument from authority).
PS What is so difficult about the packaged chip test? At the very least measure the supply current to exclude the meltdown risks and run just a few test vectors through them to check the I/O protocol works. They are in way too much of a hurry to get product shipped.
PPS "The chip manufacturer I believe is chosen today. Sam was quite matter of fact about how they aim to hit September,"
... nothing more needs to be said. Read it and weep.
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My takeaway from that ... There is no wafer test. There is no packaged chip test. They are simply going to solder the chips on the boards and hope any defects are not fatal (ie unusable boards). Their yield had better be pretty good for that strategy to work. (Disclosure, my first job in ASIC industry: test engineer, though things may well have come on a bit in the last 30 years). (Ignore, argument from authority). PS What is so difficult about the packaged chip test? At the very least measure the supply current to exclude the meltdown risks and run just a few test vectors through them to check the I/O protocol works. They are in way too much of a hurry to get product shipped. PPS "The chip manufacturer I believe is chosen today. Sam was quite matter of fact about how they aim to hit September," ... nothing more needs to be said. Read it and weep. |
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