The Open Source FPGA Bitcoin Minerhttps://github.com/fpgaminer/Open-Source-FPGA-Bitcoin-MinerKintex 7 K325T Maximum Performance: 400 MH/sCyclone 4 C75 Maximum Performance: 109 MH/sSpartan-6 LX150 Maximum Performance: 100 MH/sList of FPGA Performance per device and configurationNote: The included configuration (for Cyclone 4), and source code, downclocks the chip to 50MH/s. 109MH/s requires cooling, and I didn't want to release something that would burn up your valuable chips.
This includes a pre-synthesized configuration file, ready to be loaded onto a DE2-115. The README.md includes easy instructions on how to load that into your FPGA and get up and running.
Please feel free to give me feedback, suggestions, critiques, and of course to submit Pull requests.Compatible Board
(and only purchase currently required):Terasic DE2-115 Development BoardNote: This is not the only supported FPGA board, but it is the only board with mining binaries and instructions currently available. The software can be manually compiled for many different chips (Altera and Xilinx) and boards. More pre-built binaries and instructions will be made available as time allows.News and UpdatesJune 2nd, 2011 - Flexible Unrolling Added
Thanks to the patch submitted by Udif, the code now supports a configurable amount of loop unrolling. The original design was fully unrolled, with 128 total round modules. By adjusting the CONFIG_LOOP_LOG2 Verilog define, you can choose to unroll to 64 round modules, 32, 16, 8, or 4. This makes the design smaller, at the equivalent cost of speed, which should allow it to run on many more FPGAs.
If you're interested in trying the code on a smaller FPGA, open the projects/DE2_115_Unoptimized_Pipelined project in Quartus. Then go to Assignments->Settings->Analysis & Synthesis Settings->Verilog HDL Input. You should see a CONFIG_LOOP_LOG2 macro setting, which you can set from 0 to 5. 0 gives full unrolling (largest, fastest), and 5 gives the smallest design. You will also need to go to Assignments->Device and choose your FPGA, and set the correct clock pin in Assignments->Pin Planner. Then just compile and program!June 12th, 2011 - Xilinx and VHDL Ports Added
With many thanks to TheSeven and teknohog, their code has been added to the public repo. TheSeven did a re-implementation in VHDL, with support for Xilinx and ISE. teknohog did a straight port of the Verilog code to simply support Xilinx and ISE. Both include Python miner control scripts, and serial port communication with the FPGA board.
I made little to no modification to their code for this first commit. If you appreciate their hard work on this Open Source project, please send them your thanks and donations!
teknohog: 1HkL2iLLQe3KJuNCgKPc8ViZs83NJyyQDMJuly 17th, 2011 - Code Updates and Minor Cleanup
teknohog's Xilinx Verilog port on the public repo has been updated. teknohog's serial modifications to makomk's code have been added as a separate project. OrphanedGland's port to Stratix devices, using VHDL, has been merged into the public repo. To top it all off, I updated the project's main README.md file, to prominently include a list of contributors and their donation addresses, because they deserve recognition for their hard work. I will modify the first post in this thread to include the same list
As it wasn't mentioned before on the first post, I am mentioning here that makomk made improvements to my base Verilog code. These changes improved both the overall performance of the design, and its area consumption, allowing the design to fit on a smaller, cheaper EP4CE75 chip. Great work makomk!August 8th, 2011 - Spartan-6 Code Added and Working, Altera Mining Script Updated
Thanks to the efforts of makomk, the Spartan-6 series of chips are now supported, and achieve the highest performance per $ of any chip. Code has been verified working on my LX150 development kit, and can achieve up to 100MH/s of performance.
The Altera Tcl Mining Script has just received a massive update. No more need to edit mine.tcl to hack in your FPGA's hardware and device names; mine.tcl will automatically detect mining FPGAs connected to the system. Pool information has been moved to a config.tcl file for easy editing. No more dependency on TclCurl, so the script should be Linux friendly now. And best of all, the console output has been cleaned up to look like poclbm.April 14th, 2013 - Kintex-7 Code Added and Working, Using The New DSP48E1 Design
I have just pushed the experimental KC705 code to the repo. Here is the project.
This is a DSP48E1 based design, and I have compiled and run it at 400MH/s. Included with this new design is a UART interface, instead of JTAG, since the KC705 kit has an on-board USB-UART bridge. See the README
for more information on how to use the UART interface. As an additional surprise, this code includes support for the Kintex's on-die temperature sensor. Temperature readings are reported over UART, allowing external software to monitor the chip. In the future I will add automatic shutdown on over-temp conditions.Contributors
These fellows have contributed to this Open Source project in various ways, and deserve recognition. If you appreciate their hard work on this Open Source project, please send them your thanks and donations!Not listed in any particular order.teknohog
- 1LbqTCA1cnpbbdKbXzZZfHYMe7teiczQc2NOTE: If you've contributed to the project, and are not listed here, or your donation address is not listed, please contact me. I do my best to keep track of everyone, but I'm only human.
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May 19th, 2011
First official release of the Open Source FPGA Bitcoin Miner.
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