Haven't heard from them since Saturday, so don't send things to me :-) . My main question to them was how do they intend to fix (hat on the mcu, swap the mcu, reprogram via jtag, reprogram using jig), number of fixes needed per board (one component or several), any traces that need to be laid/landed, and number of boards to figure out if/how/what cost I can do it.

Meantime there are always Titans to fix :-)

*nod* Looks pretty simple, they don't have to swap the chips (which is a pain) which is good.

C

Yes, I'm in the US.

C

Sure. Would be happy to help.

It's a B+, but I think their code was developed on a B unit. The earlier B+ units could support the code releases from KNC, but those boot images will not work with RPI3 or (this is what I seem to be running into here) later model B+ because the video chip (which does the IPL loading) is different.

Add that to Rpi changing how SPI devices are enumerated and zero development on the KNC code and you have a bit of a problem.

C

How did he replace the molex pins? Can you shoot a pic of the front and back?

Pins 1,3,5,7,9 should not have low resistance. If you see low there then the buffers are damaged.
Pins 4 and 6 are the power supply pins for the main chip logic. If either is shorted you're sunk.
Test relative to ground (the top pins on the Molex).

Cube either has shorted CPU lines or blown buffers. Can you check resistance with a meter between each of the pins on the 10 pin connector and ground?

The qberty board has a short on its' 3.3 volt line where it runs through the crystal. That keeps the Pi from even powering up (and might blow up the Pi if your PSU was big enough). I've cleared the short on a test board, but am also fiddling with the crystals.

C

I'll put some time on it this weekend, been testing your cube (the cap is back on, the solder was bad, 64mh as seen below) and on a separate controller Johnny's (fun little project, was totally dead, now running fine but occasionally resets the power supply. Run it on its' own supply and it is happy). His other cube is a mystery: Supplies now come up (two shorted), communications restored, but the chip doesn't hash.

As for the BB's I was waiting for a need for more fpga's so I don't do a 5 buck order. Sure enough got another one in for fixing, so order going out for higher pf crystals.

C

 bfgminer version 5.4.2-titan-2.02 - Started: [2016-12-02 20:21:48] - [  0 days 17:18:49]
 [M]anage devices [P]ool management Settings [D]isplay options                                                                               [H]elp [Q]uit
 Pool 0: us.litecoinpool.or  Diff:125m  +Strtm  LU:[13:40:26]  User:Well yeah, right....
 Block: ...2a7ab326c9461e01  Diff:67.7k (484.8G)  Started: [13:38:43]  I: 1.22mBTC/hr
 ST:21  F:0  NB:411  AS:0  BW:[ 24/ 14 B/s]  E:0.77  BS:485
 1/4           | 66.05/64.25/64.14Mh/s | A:7304 R:42+0(.57%) HW:1207/.50%
-------------------------------------------------------------------------------------------------------------------------------------------------------------
 KNC 0a:       | 13.98/13.57/13.57Mh/s | A:1543 R: 6+0(.39%) HW: 203/.40%
 KNC 0b:       | 10.91/13.59/13.56Mh/s | A:1514 R: 9+0(.59%) HW: 221/.44%
 KNC 0c:       | 24.05/18.56/18.52Mh/s | A:2146 R:14+0(.65%) HW: 415/.60%
 KNC 0d:       | 19.57/18.52/18.48Mh/s | A:2102 R:13+0(.61%) HW: 368/.53%
-------------------------------------------------------------------------------------------------------------------------------------------------------------
 [2016-12-03 13:35:56] Accepted 0005a5a2 KNC 0c Diff 177m/125m

Someone pls take a pic of both sides of the board and post to imgur. Also take a pic of the CPU chip on the board close up I want to see what other components are around it in the event we have to pull and swap parts.

If the question is removing/replacing the chip in the upper left corner it's doable, but will require air tools, good flux, and a preheater. I can do this with the tools I have if needed.

However I'm a bit surprised you can't just use a jtag programmer to re-flash the chip.

That's a problem. I put the BB port on the side for a bit, if someone really wants me to blow a weekend hacking a version of Debian/Pi that will boot let me know.

Ah, hm. I wonder if the "jig" is something like an AVR Dragon, like we used to reprogram the Atmel MCU's on the Jalapeno and Singles using a JTAG interface....

Is there a 10 pin diagnostic port on these things?

Neat. Any chance someone can post pictures of the gen 1, 2 and 3 boards, along with the controllers. Curious if there are any board specific changes.

This is actually an interesting line of analysis: Can someone stick one of these in a snowbank or a freezer? I'm curious if design issues in the power supplies or the board layout is resulting in heat plus resistance knocking down the SPI lines.

C

I was thinking more hotspots on the board itself. That's a long distance to freight x amps at low voltage, the issue can pop up where voltage instabilities between dies can lead to virtual ground loops on the SPI signal interface (to its' ground assuming it's not isolated).

The power supplies themselves look to be the same concept as the old jalapenos right down to the 1850 running two channels of FETs feeding the same supply line.

Interesting.

Well that's a weird way to do it. 1850 linear power controller, two high side/2 low side Fets (bad idea), and they're really hauling the power to the dies. I wonder how much interference that's causing.

What does the board look like with a thermal camera? Hot spots on the way to those hashing chips?

Ain't that interesting?

Hm. So a chip throws an invalid nonce (typically a comm error) and the other chips jam. I wonder what kind of recovery/isolation code is in place to detect this, isolate the errant chip, and resume the queues on the rest of the die. Does Cgminer allow you to turn off queueing of work to processors?

Likewise you should be able to use tee or something to tee off the full diag logs to a big fucking file, then grep around in it.

Fun, hm?

Just for giggles, try running a bitcoin full node on the Pi and see if the miner drops a lot more. What kind of Pi are they using, fastest around or some slow slug.

Hm. How about when you turn on full diagnostics in CGMiner. Before the board resets, do you ever see anything odd like got Nonce for invalid hash, or stuff like that which might indicate chip cores are yammering on top of each other?

When the dies come back do you once again get invalid nonces coming out of them (meaning the dies reported stale work) or do they just pick up and hash (indicating the dies lost power and reset their buffers)

Any links to close up pictures of a board? How do they have the power laid out between the DC-DC's and the chips?

Edit: I see the nonce error. Interesting. Pi's suck at SPI by the way, they should have used beaglebones. This points away from a power supply dc-dc issue at the moment. Hm.