Normally, IOREF is set with a restistor divider to half IOVDD (normally 1V8). To make the board simpler, IOREF was connected to core voltage.  Core voltage was adjusted between 0V59 and 0V83 V and operation of the chips remained normal. Leszek/bitfury, can this be done on the miner board also? Reduces the wiring a bit. intron |
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Latest test was done to maximize performance, while keeping chip temperature below 50 degrees C. A small heatsink was mounted on the bottom of the PCB, and cooled with a fan to control the temperature. Internal oscillator set to slow mode, using { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x3F, 0x00 } configuration, which is slightly faster than bitfury's example code. Vcore at 0.835 Volts, resulting in 2.5A current (2.1W). Clock frequency of 230 MHz. Instead of bitfury's test vectors, a test was done with 2048 more or less random vectors. Based on 756 cores, a yield of 1512 valid hashes would be expected, but 1511 were found, so COP is very close to 1. Net hash rate would be almost 2.7 GH/sec @ 0.8W/GH. With one extra clock bit, core clock increased, but COP ropped to 0.94, resulting in lower net hash rate. http://imgur.com/g7UTw6VGreat results! Thanks! Hopefully tomorrow Leszek will send more chips, and we'll know more data! But take care of power noise. We still need to find out how to chain the SPI bus. The bitfury S-HASH mining board layout is ready, waiting for funds to get it etched. Leszek is working on this. When this board arrives we finally can put 16 bitfury's to work simultaneously:) intron |
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Latest test was done to maximize performance, while keeping chip temperature below 50 degrees C. A small heatsink was mounted on the bottom of the PCB, and cooled with a fan to control the temperature. Internal oscillator set to slow mode, using { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x3F, 0x00 } configuration, which is slightly faster than bitfury's example code. Vcore at 0.835 Volts, resulting in 2.5A current (2.1W). Clock frequency of 230 MHz. Instead of bitfury's test vectors, a test was done with 2048 more or less random vectors. Based on 756 cores, a yield of 1512 valid hashes would be expected, but 1511 were found, so COP is very close to 1. Net hash rate would be almost 2.7 GH/sec @ 0.8W/GH. With one extra clock bit, core clock increased, but COP ropped to 0.94, resulting in lower net hash rate.  |
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Hehe, of course we knew that, there was also a Link to the Blog where pictures of the actual chips are^^
But thanks
 I was just bored a bit, hihi:) |
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ok here we go:
burnin, do you plan on posting scope traces of actual Avalon signals? Highly interested in the REPORT_x timing for starters. And you are brave to dead bug a QFN48, hats off for that:) intron |
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Worden er ondertussen al ASIC's gebruikt om bitcoins te minen? Of is iedereen nog op de machines aan het wachten?
Ja, USB Block Erupters en o.a. die dingen van Avalon en BFL. http://imgur.com/nouiUbiintron |
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Rotterdam hier Al sinds februari aan het wachten op mijn batch #2 Avalon Asic. Hi phoenikx, Ik zit in batch vier, moet dus nog langer wachten. Hoeveel heb je er besteld? Kan ik er een paar van je kopen als je ze veel eerder ontvangt? Ben een miner aan het bouwen zoek nog Avalon samples: http://imgur.com/s7vQDziintron |
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Picture of the FXLP34P5X 1V8 to 3V3 level shifter performance: http://imgur.com/9bII5tcBlue trace is the 1V8 signal coming from the bitfury ASIC, the yellow one is the 3V3 signal going to the ARM processor. Nice, crisp signals, only a small output delay can be seen. So no worries here... intron |
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Got bitfury's SPI code working, needed some porting to the smaller
ARM processor, and the ASIC responded nicely. Voltage was adjusted
to 0V64, yielding a current of 1 A. Clock was measured, 116 Mc.
bitfury's testvectors were applied to the ASIC and 100 vectors
gave 145 results, not unlike the result bitfury himself got.
The level shifter in the original schematic works just fine,
so I guess there is no need to fall back to analog pass logic
tricks:) To be safe core power was applied first, then IOVDD.
This was done manually, will be automated in a later design.
intron | c-scape
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Hi bitfury,
Saw in your code you are clocking the SPI chain at 200 kHz:
speed = 200000;
if (ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed) < 0) { perror("Unable to set WR_MAX_SPEED_HZ"); close(fd); return -1; }
if (ioctl(fd, SPI_IOC_RD_MAX_SPEED_HZ, &speed) < 0) { perror("Unable to set RD_MAX_SPEED_HZ"); close(fd); return -1; }
Why it is so slow? Just te be sure during development or are there other reasons?
It's not a problem, just curious.
intron
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You were right bitfury, the initial input level shifter circuit was not working correctly. Seems the the parasitic capacitance of the 1V8 zener together with the 1K input resistance caused severe detoriation of the waveform due to the RC-delay. Redid the circuit: increased the current by lowering the resistance to ground and replaced the zener with a 3V3 type connected directly to in the inputs. Did also some measurements, looked not that bad. Inputs SPI signals are divided to 1V8, output SPI signal is level shifted to 3V3. See image:  This is still with a bare board, no ASIC yet. Might need to lower the restistors even further to get crisp edges. Will first look into the SPI code now. intron |
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Did some experiments with forced air cooling of my USB Erupter. See attached plot, what a little USB powered fan can do: http://imgur.com/co3Z0uFintron |
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6 sample Avalon chips arrived today from zefir. Test PCB boards are ready , most of the components are here too.  Sleepless nights are comming Nice:-) intron |
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why don't we just ask BFL about who produced boards for them?
that place can easily produce them again since they've done it already, no?
Is the firware or when there is a FPGA the FPGA object file available from BFL? Otherwise you end up with just the bare metal and not a functional miner. intron |
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Has anyone put a cro or logic analyzer on a real Avalon? Without any of their hdl it is tough to know what the comms looks like. Not releasing their code is annoying, they could release what they can and we could check out the comms protocol even if we can't build chips. In a few months their ip will be useless.
Asked the same, no response. The datasheet is rather vague on crucial points, would love to see some real life scope traces. intron |
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First I would like to say that chip is working. Complete confirmation using test-vectors.
Nice. intron |
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Got the bootloader to work on the ARM and soldered the power switch between the 3V3 net and the input of the 1V8 regulator that generates IOVDD. Can now control IOVDD from the command line:  intron |
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