First I would like to say that chip is working. Complete confirmation using test-vectors.

https://mega.co.nz/#!yVMTTCSA!SFsVTAWeMSnxwUeuRnwR0Wm_d74xVyOdxkL5LEI_LsQ

Here is SPI code to download and test code.

Then - measurements of error rates and real hash rates were performed using 100 first test vectors (as enabled in code), no board cooling (that's pretty impressive - it works on PASSIVE board made by Rene - great thanks BTW - you may use code I provided to perform same tests... Maybe just oscillator should be adjusted - on OUTCLK you'll see clock and you should bring INCLK and OUTMISO to ground while testing).

Results so far

0.596 V, 125 Mhz, 100 tasks sent, 122 solutions got, COP is 0.84 (122/145), Ideal 1.45 GH/s, Real 1.22 Gh/s

0.596 V, 150 Mhz, 100 tasks sent, 19 solutions got, COP is 0.13 (19/145), Ideal 1.74 Gh/s, Real 0.23 Gh/s

0.596 V, 78 Mhz, 0.6 Amps, 0.36 W, 100 tasks sent, 145 solutions got, COP is 1.0, Ideal 0.91 GH/s, Real 0.91 GH/s, 0.39 W/Gh/s

0.596 V, 45 Mhz, 0.39 Amps, 0.23 W, 100 tasks sent, 145 solutions got, COP is 1.0, Ideal 0.52 Gh/s, Real 0.52 Gh/s, 0.44 W / Gh/s

0.596 V, 96 Mhz, 0.725 Amps, 0.43 W, 100 tasks sent, 143 solutions got, COP is 0.986, Ideal 1.12 Gh/s, Real 1.1 Gh/s, 0.39 W / Gh/s

Please note that it seems that 96 Mhz is close to _BEST_ solution... Then I started to increase voltage, while not changing internal oscillator settings - it is not power-stabiized and its oscillation frequency

should follow and grow up. What is most interesting (and this should be confirmed later - this is INTENDED operation) - that oscillating frequency increases, while error rate remains the same as transistor strength in oscillator and interconnect variances within same die are less.

0.7 V 140 Mhz 1.2 Amps 0.84 W 100 tasks, 143 solutions got, COP is 0.986, Ideal 1.63 Gh/s, Real 1.6 Gh/s, 0.52 W / GH/s

0.8 V 180 Mhz 1.87 Amps 1.49 W 100 tasks, 139 solutions got, COP is 0.958, Ideal 2.093 Gh/s, Real 2 Gh/s, 0.75 W / GH/s

0.9 V 214 Mhz 2.62 Amps 2.36 W 100 tasks, 132 solutions got, COP is 0.91, Ideal 2.48 Gh/s, Real 2.26 Gh/s, 1.04 W / Gh/s.

Not tested more... And likely latter was worse due to not enough cooling.

We do not need more just confirmation testing that it works, but we need more extended testing like that. So I'll discuss tomorrow with Leszek and we'll send test chips, and will ask to perform tests and post your results. Also we likely will make some contest for say - best USB-stick (most of hashing power with smallest form-factor), highest hashing rate (real, not ideal, crunching clocks is not a problem), etc.

I would like to note that THIS design thanks to much effort spent in Monte-Carlo sims with flip-flops works really well at low voltages :-) Small error rates and no flip-flop losses like it may happen with logic cells unqualified for low voltages. It scales almost like it should in theory, not like it does in practice when cells are unsuitable and you simply can't go lower because frequency will drop DRAMATICALLY. This enables application of this chip for different kind of heating devices where voltage can be changed in dynamics to adjust produced heat to requirements, etc etc etc.

Also I am preparing to execute payments to all betters, because it is clearly our fault that we failed to meet deadlines. It is too cumbersome to calculate actual bet amount, so I would pay off using averaged multiplication value about 1.86 or so (I don't remember exactly have to look in my calculations).

Thanks that we ordered more wafer count - we now can fulfill say 100 Th/s operations, etc :-) So there's nothing to worry. And we can start planning for further testing and production.