Any info on their turn time & shipping options? |
|
|
|
Alsp, you have lost like, 300MH/sec of hashing power, in 3 days. How can you say, no problem? BIG PROBLEM
the whole network is losing hash power as people move back to litecoin after the difficulty readjustments though |
|
|
|
Am I assuming we won't be doing lead-free?
i think it's critical to use 63/37 as it will reflow at the lowest temp and has much better wetting |
|
|
|
|
You do both, is the thing.
The internal ground and the heatsink on the bottom work in parallel to lower the temp better than either alone could
Frankly i'd be very suprised if Avalon's reference PCB doesn't use this technique.
|
|
|
|
The 1/2oz layer is not for heatsinking.
The pad under the ASIC is a ground pad the heat transfers thru the 16 via to the bottom ground plane.
Yes, but you better spread heat with an internal ground layer directly connected to all of the vias, if you look at those application notes it's standard practice. you do this along with copper on the bottom |
|
|
|
|
Yeah so you can't get coins out? I put my wallet in, just deletes what i put in.
and i have just slightly over 200 something FTC
fucking awesome, again, the wallet will go 0->200 and back to 0.
|
|
|
|
...
nm, make sure you have libminiupnpc-dev
is this for me or? No, i answered my own question about why it wouldn't build on linux. |
|
|
|
I would suggest a higher density of vias for the thermal pad. Here is an example of ones that we do for power drivers.
I could easily increase it and I may still. My brief research indicated 1.5mm spacing as optimal. It may be worth spending $10 for test boards with 15,25,36 via pads and a bundle of 1/2W resistors placed around the pad body to simulate, before ordering final boards. Or with the prototype board use one bank of 16 and one of 25 to test difference. If you can, i'd recommend adding fiducial markers on the silkscreen, both a few on the corners of the board, and local ones by each QFN [dot by pin 1]. for the board ones you can do a circle of copper on the top layer (with no soldermask) as well
Also i've been reading a few design notes on QFN heatsinking - it might be worth using 2 or even 3oz copper on the internal ground plane for added heat conduction, but i need to do some testing more more reading - just something to be aware of
How are you doing the layer stackup? Which layer is the power/ground plane?
Definitely plan to add and the silkscreen now is just what Kicad did by default. I haven't looked at it yet for adding what I want and removing garbage like "PIN1". I was working with a rather basic 1.6mm stack: top 1.2V plane, 1oz 0.2 FR4 inner 1 3.3V plane, 0.5oz 1.2 FR4 inner 2 signal, 0.5oz 0.2 FR4 bottom GND plane, 1oz But there is more GND planes under the switching supply, and a few signals escape on inner 1. I'm open to suggestions but something unusual will push the board cost up. Part of keeping the cost down is that they batch with other boards, so go weird and it will likely push cost by 5-10x or more (for short runs anyway). I'd consider using a thin board to help heat pass to the back more easily and I can go 1.2mm total for the same cost. I'm just unsure of the downside to that. What do you mean spend 10$ for test boards? The setup cost is usually several hundred dollars. also, any reason you don't have an internal ground plane? I'm only familar with a 4 layer, 1 Vcc, 1 Gnd setup, where typically the signals are routed on the top and bottom only if at all possible, and the middle two layers are reserved for ground and power. The unused portions of the bottom layer can then be flooded with ground plane as well to facilitate heat transfer, especially around the QFN. the top layer can be flooded with the 1.2V plane or mini-planes I think it may be very important to have internal ground plane that the QFN is directly connected to. |
|
|
|
|
anyone get errors trying to build the qt client on linux?
nm, make sure you have libminiupnpc-dev
|
|
|
|
For ROI calculations, I ignore the exchange rate and use this simplified formula - It's not exact, but it's a quick way to do it:
Cost = 1.99 btc
Network Hash Rate = 78,000 Gh/s
My hash rate = .3 Gh/s
My Share of the Network = .3 / 78,000
Blocks found / day = 144
Block Reward = 25
Therefore, i will earn:
.3 / 78,000 * 144 * 25 = 0.013846154 BTC / day.
My ROI in days:
ROI (in days) = 1.99 / 0.013846154 = 144 days. about 4 3/4 months.
This doesn't consider an increase in network hash rate, which I estimate will cut profits in half every month until October. Considering difficulty increases the ROI is a little longer than 1 year.
This seems about right for retail cost, it seems a bit expensive at wholesale. Ideally, I'd like to see about a 1.5 btc wholesale cost.
If this key is not efficient enough ... what about all the GPUs that are a good proportion of the network ? ASIC is coming... but at what speed ? transition is not going to be quick. ASICMiner being the fastest, followed by DIY project for avalon chips. bfl ... is going to be soooo slow ... there will be far more hashing powered added by asics than is taken from GPUs keep in mind, mining litecoin / etc scrypt-coin, and simply trading them for BTC, has been consistantly more profitable than mining BTC for months now. In fact i don't think it ever was NOT more profitable. |
|
|
|
For ROI calculations, I ignore the exchange rate and use this simplified formula - It's not exact, but it's a quick way to do it:
Cost = 1.99 btc
Network Hash Rate = 78,000 Gh/s
My hash rate = .3 Gh/s
My Share of the Network = .3 / 78,000
Blocks found / day = 144
Block Reward = 25
Therefore, i will earn:
.3 / 78,000 * 144 * 25 = 0.013846154 BTC / day.
My ROI in days:
ROI (in days) = 1.99 / 0.013846154 = 144 days. about 4 3/4 months.
This doesn't consider an increase in network hash rate, which I estimate will cut profits in half every month until October. Considering difficulty increases the ROI is a little longer than 1 year.
This seems about right for retail cost, it seems a bit expensive at wholesale. Ideally, I'd like to see about a 1.5 btc wholesale cost.
Difficulty was estimated to be 70 million by the end of july even without these. |
|
|
|
|
I guess running a pool and stealing coins is the hot scam of 2013.
Is there a trustworthy one?
|
|
|
|
I would suggest a higher density of vias for the thermal pad. Here is an example of ones that we do for power drivers.  Definitely if possible, but there's a diminishing return for # of vias though, something around 12-14 vias for a 7x7mm QFN. Going to say 25 might only be a 10% increase I'll try to put together some links to design guides on these and thermal analysis. It would be very nice if we could vary the clock and core voltage in case some of the chips have a worse thermal resistance than others and heat up -- mostly for DIY people who will get inconsistent reflow between the thermal pad and the PCB. they could at least declock and/or de-volt the QFNs so they don't burn themselves up. better to have 50% output performance than 0%. |
|
|
|
|
Hm, wonder how this compares in $/hashrate and BTC/hashrate compared to even avalon batch #3
|
|
|
|
Here's a teaser. I've done just about as much as I can for the moment. I could tidy it up a bit and make some bits more pretty. If I recall correctly this is the top and bottom layers with solder paste. The middle layers aren't shown. Note that data signals will be on a middle layer. And I'm still playing with the connector area. I may put pads for an SMD barrel jack at board edge next to PCIe power so that those who want no thru holes (due to heat sink) can use that. I could find no SMD mount PCIe connectors so best bet there is to drill the heat sink or put copper pads between it and the board. Kind of a nuisance really. I should have changed the name of that silly 1PIN hole footprint.  If you can, i'd recommend adding fiducial markers on the silkscreen, both a few on the corners of the board, and local ones by each QFN [dot by pin 1]. for the board ones you can do a circle of copper on the top layer (with no soldermask) as well Also i've been reading a few design notes on QFN heatsinking - it might be worth using 2 or even 3oz copper on the internal ground plane for added heat conduction, but i need to do some testing more more reading - just something to be aware of How are you doing the layer stackup? Which layer is the power/ground plane? |
|
|
|
|
They're the NSA. If they wanted, they could spend <1% of their budget, have some nice 28nm ASICs fabbed and mass produced and take like 80% of the network.
Good news though. They don't give a shit.
|
|
|
|
Avalon's confirmed orders of chips ALONE are going to quadruple the network hashrate. Add in the other ASICs, difficulty will be between 6x and 10x+ higher, and prices seem to be dropping down Yes, understood. That's why I specified "at current difficulty" I did forget to change the exchange rate to current exchange though. At any rate, I think anybody who has seriously run the numbers with the intent of buying these chips knows that we're looking at a difficulty of 40-80million by the time we all get up and running. Even so, if you presume a difficulty of 80Million, and an exchange rate of $90/BTC, 500 chips still generates $2500/month. I'm guessing that both those numbers are on the upper end of 'bad-case' scenario, and we're probabaly more likely to jump in at about 40Million when these things start coming online, which should give a window to recover initial investment costs relatively quickly. But time is of the essence. Realistically, if we don't fund this thing by this time next week, we're DOA. So hope for some more big investors, or that BTC temporarily drops to $10, and I'll be in for 48BTC per day until it funds.  The best estimates have difficulty @ ~65-70 mil by the end of July (roughly 3 months). If the chips do arrive in 10 weeks, and you've managed to get fab and testing done and it only takes you 2 weeks for assembly and shipping then starting your estimates from there isn't horrible. If a batch costs 50/50 chips to board, you're looking at BTC1560 initial outlay (minus support gear, ie host, power supplies, etc). If it's as efficient as Avalons you're lookin @ about 28.2 kw/h to operate. Assuming a 25% Network Hashrate Increase per difficulty, with electric costing you $.115 you're looking at about a 7 months for complete BTC principal repayment, not including cost of electricity ($13,664). If you were to count electricity, you would be $8,402 short when after 8.4 months difficulty became so high you paid more for electricity per time period than you received in coin (assuming $105 exchange rate). Something to note however, Give the above is accurate: the network hashrate would be 19,317TH/s (27,895% increase from what it is now) Difficulty would be 2,698,676,748 (26,103% increase from what it is now) So the question is, do you think 19,247TH/s worth of gear is going to be deployed between now and Jan '14? *Disclaimer: I purchased a batch of chips. do you have a source for those ~70 Million difficulty at the end of july quotes? |
|
|
|
It's been selling for $10k. How much does it cost to produce those?
It would cost tens of thousands to millions to produce TONS of asics. Avalon uses TSMC to make the chips it seems. ALTERA and XILINX use TSMC to make their asics and FPGAs as well. a 130nm ASIC seems very old school technology, so I am guessing the cost was in the thousands to Hundreds of thousands of dollar range. When you get to 13-28nm asic...then we are talking millions. Again this is all speculation from myself working with Engineers, Managers, Directors, VPs and CEOs in the Semiconductor industry. 13-28nm is billions. That's basically only Intel CPUs (and AMD @ 28nm) |
|
|
|
|
Show Posts
