Sergio Demian-Lerner has discussed this in February of 2015 on his blog:

https://bitslog.wordpress.com/2015/02/17/faster-sha-256-asics-using-carry-reduced-adders/

Basically it is an interesting idea, but neither Sergio nor those 3 guys discussed how it could be affected by the overall pipeline design. It seems like those guys from UIUC considered only one (or maybe two) pipeline layouts (the alternate drawn in dashed lines).

Much better science would be to consider way more pipeline layouts including something extreme like 32-way pipelined ripple-carry-adder that adds two 32-bit integers in 32 clocks. It seems slow, but the area is unbeatable. At least those guys explicitly discussed area*delay products. But it doesn't seem like they carried this to the ultimate conclusion of power/hash rate and area/hash rate (or better yet price/hash rate).

But it is the only paper that I've seen that was actually brave enough to include the plain ripple-carry-adder (RCA) in the final comparison tables and graphs.

I'll correct myself, before somebody else corrects me.

The address used in the genesis block is actually currently worth BTC16.17850597  .

Many people did a voluntary offering or donation to that address, sort of like a tribute to a god. Currently there are 1027 such tribute transactions. Those are spendable.

It is more interesting than that. The genesis block is worth 0BTC because it is unspendable due to a quirk in the core implementation.

Whether the quirk is an unintentional bug or intentional decision is still being discussed.

Really, it isn't my problem that you can't understand this. Even garage miners understand that selling the old miners on eBay (or to Venezuela) and replacing them with new ones is part of the ROI optimization strategy. I think ASICMINER was the first who did that on industrial scale.

Not really. This is well known since the days of GPU mining. Each board has two optimum operating points:

1) max GH per board, overvolted and overclocked, thermally limited

2) max GH/J per board, undervolted and underclocked, simultaneous-switching-noise limited

One quick look at the photo of the 28nm board shows that there's plenty of open space and wide copper traces to allow air cooling without the need to install heathsinks. When compared to rather dense Spondoolies' boards this is quite obvious that Bitfury's design has much wider thermal margins.

With those board it looks like point (1) is achieved in the immersion bath and point (2) with forced air cooling but without heathsinks.

This is just nonsense. In particular "retrofit of 28nm boards". Those boards obviously don't need retrofitting (immersion to forced air) because of rather low power density. The opposite would be true for air to immersion move: remove heathsinks and fans, extraordinary deep cleaning of flux residue and lacquer layers, possible need to replace the components that leach something in the Novec bath. The only retrofitting required for immersion to air move is a trivial reprogramming of the voltage and clock operating points in the controller.

I'm positive that nearly every MBA-level course has some examples of how to optimize the utilization of the working capital. Usually it is done with some historical examples like a move from steam power to diesel power in railroad locomotives. I'm not going to reproduce it here.

Oh, c'mon. It would be a waste of immersion bath to run old underclocked miners.

And what it means "paid for"? Presumably Bitfury used either its own or borrowed capital to populate their immersion cooled facility. Selling them would actually release working capital to spend it on manufacturing new generation miners.

Why? The whole point of immersion cooling is that it allows using the same boards design as for air cooling. The difference is only in how far the board can be overvolted/overclocked for optimum GH/$. Theoretically the buyer would air cool them to optimize GH/J, which means undervolting/underclocking.
 

Thermistor wouldn't work without calibration which would be additional expense in testing.

But some simple circuit with diodes or BJTs using reverse polarized junctions could have sensible accuracy without additional calibration.

The problem is how to come up with a sensible benchmark.

For example the block & transaction storage was obsessively benchmarked with the time it took for the initial load to certain block height. The end result is that it is over-tuned for that operation but performs rather badly for the regular everyday "add one block worth of transactions to the indices" operations. The original BerkeleyDB code was capable of finishing that task faster than the current LevelDB code. The LevelDB code gets bogged down in premature reorganizations of its storage levels that will be redone in few more blocks, without amortizing the cost.

It is kinda like file system benchmarked only for chkdsk/fsck and ignoring most of the everyday operations with frequent mounting and unmounting between relatively rare integrity checks.

It sure would work, but it is an overkill.

The ultimate mining power supply is essentially a welding rectifier with some more ripple filtering and arc-start disabled. The normal welding rectifier have some very coarse regulation operating at line frequency (50Hz or 60Hz), not in the kHz or MHz ranges of precision voltage regulators used for non-power electronics.

With such power supplies your at-the-wall GH/J will be the same as at-the-chip GH/J within the normal measurement and process tolerances.

If any home experimenter reads this message: I'll reiterate the necessity of disabling the arc-start circuitry of the normal welding rectifiers. They intentionally produce higher voltage when the output current is near zero, then rapidly drop it to the nominal output voltage once the electric arc starts.

I think you are both missing the point of the 48V DC supply. Somewhere between 25V and 50V there's a point where power no longer needs to be regulated. It is sufficient to just rectify and ripple filter it. With lower voltages you cannot risk it because accidental overvoltage will permanently destroy the oxide layer on the chip. With series/string implementation backed by some sort active voltage divide balancing you get enough oxide layers in series to be no longer afraid of surges. There's enough margin between the normal operating point and the breakdown voltage.

Nobody cares for under-voltages or sags. They just cause momentary increase of erroneous results.

The only thing that requires regulated power supply (and uninterruptible power supply) is the mining controller. But it has negligible power requirements compared with the hashing engines.

Remember that coin mining equipment isn't really a computing equipment or telecommunication equipment. You can reset it as often as you like and you never store any information for more than milliseconds.

Yeah, keep misdirecting the answers and pretend that you don't understand them or that readers misunderstood you. At your level in the company hierarchy this gives more information to the potential buyers or partners than an audited accounts statement would give.

It would be the most delicious irony if in the end we (readers) could figure out that Head of Development actually can't give an answer without consulting some subordinate.

We'll live, we'll read what you post, we'll see. You are on a notice.

I'm so glad that I'm not financially associated with any of the Bitcoin operators and don't have to be afraid to ask the impolite questions.

Actually that is bullshit. Bitfury_POWER has around 40 pins, most of them non-obvious.

Will you actually dare to disclose what the PARITY pin does and what is the function of the two associated LEDs?

The 4 pdfs posted thus far are of nearly zero educational value. They are just top level board schematics without the description of the pin functions of Bitfury's proprietary chips. Without that information they may be of some value to a reverse-engineer, but as a general technical information source their value is zero.

The one-line bitfury post from nearly 3 years ago contains more technical value, because it shows the internal topology of the input and output stages of the still secret original bitfury chips.

There was more information posted in 2013, but is all inaccessible because at that time bitfury used mega.co.nz file locker which is now gone.

So the most of the educational value you get from the above post is:

1) Bitfury uses separate chips of their own design made in 250nm process for signal distribution and gathering (thicker oxide -> higher supply voltage)

2) Any competitor who still uses high-current buck converters with on-board magnetics was and will be significantly undercut by Bitfury purely on the cost of 3rd party components.

That's about it.

I welcome any comments from anyone who may have recognized the circuit fragments using discrete BJTs, MOSFETs and OpAmps and could post some links to the full circuit schematics including the on-chip interface stages.

You need to learn prerequisites first:

1) digital logic design (combinatorial and sequential logic, synchronous and asynchronous circuits, automata theory, etc.)

2) elements of circuit theory (nodal analysis, mesh analysis, you'll need to understand what SPICE will do for you and what it won't do)

Only after some understanding of the above you will be able to comprehend the CMOS ASIC design textbooks.

For somebody who is a self-starter the best way is to get some low end FPGA kit from e.g. Digilent or Avnet or Terasic. Low-end because those are supported by the free editions of the respective design toolchains. This is the main objective: to actually understand the methodology and limitations. When FPGA's were competitive for Bitcoin mining several members of this forum learned everything from scratch in about 3 months.

The classroom environment becomes important only later. You want to choose a school that has access to the https://www.mosis.com/ prototype fabrication service.

Bitfury actually did his first chip in partnership with some Polish research institute when I pointed to him that he will then qualify for http://www.europractice-ic.com/ which is an European equivalent of USA's MOSIS.

Somewhat naïve, but at least doable. Essentially 21 Inc's mining chip works like that, but designed by somebody more experienced in DRM (digital rights management).

All of it, I mean all that you can come up with. You have this big target painted over your faces: I want to buy Bitcoin turboencabulators, I'm ignorant of the technology, please rip me off.

Cypherdoc was exactly like you, he was ripped off on his Bitcoin turboencabulators by Hashfast, but actually made money by shilling and roping more naïfs.

There are three ways of getting something done:

1) learn how to do it and do it yourselves;
2) learn who can do it for you and for how much, then pay it;
3) prohibit your teenage children from doing it, and hope they will turn like all teenagers and do what's prohibited.

What I see in both of you is the strong desire to not learn anything about logic design and the semiconductor industry. Sidehack is one step ahead, because he is at least openly willing to admit that he won't do it.

You are like two guys who want to win competitive dance or acrobatic event, but don't want to get their asses off the lazy chair. Learn how to walk and tap your feet with the music before you sign up in a competitive event.

Edit: anyone here remembers that guy who was claiming to develop ASIC simultaneously with BFL? I forgot his handle on this forum. He was hiring people for the assembly and shipping departments, rented the premises, but his RTL wasn't even through the simulation stage.

Edit2: All right, I've found it: it was cablepair. He successfully shipped ModMiner (somebody's else FPGA design) and failed to deliver bASIC, but returned at least some of the collected money. That was about 2012. Now we have 2016 and another experienced telephone technician is trying to start another fabless ASIC boutique.

Edit3: Maybe somebody remembers who was that Arab guy living in England with experience in fashion for Islamic women? He was also trying to do the same.

Yeah, this is a good point to emphasize. There were several counterfeit FTDI chips. All of them used much larger and more complex SoC chips with single fixed program to emulate the real FTDI. The large SoCs were cheaper because they were manufactured in much larger quantities and had multiple competing sources.

The main value of the real FTDI's is in their much higher immunity to noise and clever design that allows for much lower bit error rates. But many designs completely waste that additional functionality. One example probably known here would be ngzhang's ICARUS board (dual Spartan 6) where he simply wouldn't bother to route any signals beyond the minimum of RxD and TxD to the FPGA. This is the reason why all the Icarus-compatible miners have so much reliability problems with the communication between the chips and software.

Trying to understand why the counterfeit using 10-100 times more gates than the real chip is cheaper than the original is a good introduction to the financial aspect of semiconductor manufacturing. Much better than throwing nearly random megabucks imaginary costs.

And the above is exactly a pitch from con man or somebody so naïve that is indistinguishable from a con man.

Bitcoin mining is full of chips designed by barely competent CAD monkeys. The access to capital is not sufficient to produce a worthwhile chip. It is the access to the required knowledge that is the differentiator.

Another symptom typical of a con man (or an equivalent naïf) is a reference to "drop and place IP blocks". No mining chip used such blocks for hashing engines. They may have contained IP blocks for e.g. clock generation PLL. But all the mining chips starting from the first ones by ASICMINER and BFL were custom RTL synthesized using standard-cell design flow. The differences in performance were mostly in the amount of tuning work done before the tapeout. That's why there's no valuable IP (intellectual property) in the masks for the obsolete chips (like Hashfast tried to sell). The intellectual property mostly consists of babysitting the toolchain through the iterations of the optimization process.

I've been there and done it. Many ASICs are designed and manufactured just for the purpose of copy protection and design security: to make coming to market with competitive product too expensive by eschewing anything off-the-shelf or available from a second source. From what I understand such nearly-empty chips are nowadays even more popular to hide the patent infringement amongst the completely bogus chip-space-filling circuits.

I don't think we've communicated. I wasn't talking about a separate, discrete chip. I was talking about using a little free space (and maybe pins) on some larger chip with completely different purpose and market.

The incremental cost of adding tiny mining test circuit would be nearly zero. For an engineer with experience in the actual toolchain used in his main project, the additional effort required to drop SHA256D miner is about one to few wasted lunch breaks. All the required expensive work will be done anyway while doing the main project. If the main project already has some scheduled design iterations the miner can ride all of them for free.

This is the way one can tell that people quoting megabucks figures have no actual technical contacts in the industry. They may have some sales or non-technical middle management contacts. The SHA256D miner is so simple that nearly all the R&D on the engine can be done for free by somebody who already has access to the appropriate tools and kits.

The megabucks are only necessary when one wants to mass-produce chips by filling entire wafers with them. The quantification of possible market is also completely different story from the R&D costs.