Cheers, no problem, its a good thing to to put interest in and just as people are interested in undervolting S3's at the moment, S5 are coming up next.
Three more 4% difficulty changes will see my most undervolted S3 with 0.64V & 125MHz giving 0.49J/GH at break even so I will be putting them on ebay as soon as I get round to it.
So moving to the changes to the V1.91 hash boards. A bit complex so needs a careful read.
1) The PCB was changed at V1.9 to make provision for multiple Xtal Oscillators, these were then fitted at the V1.91 rev. In all the earlier boards there was a single Xtal on the bottom chip in the chain and then the clock signal was then chained through the 30 chips.
V1.91 has 4 Xtals, the original one on the bottom chip in the chain and then an additional Xtal after every 4 chip pairs.
As this is a cost addition I am sure that Bitmain must have had a good reason to fit the additional Xtals. Why this might improve operation when the miner is undervolted I do not know? However it is a contender for the improved performance.
2) Second change is a strange one. In the original design each chip pair in the chain had an LDO Voltage Regulator that supplies the PLL and IO circuitry.
The LDO was fed from the Core voltage of the chips 3 steps up the chain. This means with a 12V supply that the voltage into the LDO is 3 x 0.8V = 2.4V. Output voltage from the LDO is 1.8V for the IO & Analog PLL with then a potential divider to give 0.9V for the digital PLL.
The LDO for the last 3 chips in the chain are supplied from a small 14V Buck Converter, this voltage, when the supply is at 12V, equates to 2V into the LDO for the last chips, 2.8V for one back & 3.6V for two back.
When the Miner is undervolted the input voltage to the LDO will reduce and with a supply of 9V the voltage into the LDO is 3 x 0.6V = 1.8V. This could be part of our problem when undervolting as the dropout voltage of the LDO is 0.3V. So this would mean that any voltage less than 2.1V would be at risk of being insufficient for the circuitry? 2.1V would be reached when the supply is reduced from 12V to 10.5V.
The change in V1.91 is to do away with the LDO's. The supply voltage for the analog PLL and IO circuitry is now taken directly from Core Voltage of the stage above. The same potential divider is retained to feed the digital PLL The last stage in the chain retains an LDO driven from the 14V Buck converter.
So now looking at some numbers associated with the new means of supplying the PLL & IO circuitry is where things get confusing in relation to their value as an undervolt enabler.
So at 12V the voltage will be Core Voltage x2 = 1.6V. This is already very close to the data sheet minimum of 1.62V but almost certainly ok. However when we are undervolted to 9V Core Voltage x2 is only 1.2V which is well below the data sheet minimum.
It is just possible that as the core voltage is reduced the chip "likes" a matched reduction in the supply voltage for the IO & PLL circuitry, or it could just be a Bitmain cost reduction?
So at this stage all I can say is that this is a significant change with a significant effect on voltages when the miner is undervolted, so again may be the key to why undervolting is possible?
What would be good to know is what have Bitmain done on these two design points in the S5+ & S7 ? Comments welcomed on any of the above?
Rich