Community Miner Design Discussion

[Megaquake]

anyone see this video?

https://www.youtube.com/watch?v=IWxn_a0dEKI

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[sidehack]

IBM made a graphene chip that does text messaging. Hadn't seen that. Also wasn't any real quantitative information in there, but it might be worth reading up on. Something like that might be commercially viable for IC mass production in another decade or so.

[2112]

Just tossing this out there to see where the cow pie plops
you said it needs high level pre conditioning of the data the actual sha hashing cores handle and that cpu-type of operation normally is not present in each ASIC. Very true now and in the past but what if say a tiny ARM core or other MC was put inside of each ASIC to do that? That would be very easy to do these days. Possibilities there?

There's now more information available publicly:

1) There's a competing patent application by Spondoolies entitled "System and method for providing shared hash engines architecture for a Bitcoin block chain" filed at the end of March of this year.

https://patentscope.wipo.int/search/docservicepdf_pct/id00000032873338/PAMPH/WO2016046820.pdf

2) There's a discussion "Making AsicBoost irrelevant" on bitcon-dev:

http://lists.linuxfoundation.org/pipermail/bitcoin-dev/2016-May/012652.html

The ASICBoost patent seems to be slight generalization of the Spondoolies' method. But their patent application is way more readable than AsicBoost's paper. That is very rare case and it puts Timo Hanke in bad light.

Edit:

3) Relevant ASICBoost patent had been apparently published almost a year ago:

https://patentscope.wipo.int/search/docservicepdf_pct/id00000029314608/PAMPH/WO2015077378.pdf

[sidehack]

Assuming Spondoolies NDAs are no longer effective since they're closed down: I wonder if that lines up with something I heard from Guy about last September or so. When they announced the new chip for SP50, I talked to him a bit about availability and was told they had changed something in the design which gave them the efficiency boost when many chips were utilized together. So a single-chip or probably even SP20-scale miner would, I assume, not approach the 0.16J/GH efficiency given for the 800-odd chip SP50. The conversation about chip sourcing ended before any real information changed hands in October when he said they were patenting the innovation.

[2112]

Assuming Spondoolies NDAs are no longer effective since they're closed down: I wonder if that lines up with something I heard from Guy about last September or so. When they announced the new chip for SP50, I talked to him a bit about availability and was told they had changed something in the design which gave them the efficiency boost when many chips were utilized together. So a single-chip or probably even SP20-scale miner would, I assume, not approach the 0.16J/GH efficiency given for the 800-odd chip SP50. The conversation about chip sourcing ended before any real information changed hands in October when he said they were patenting the innovation.

I doubt any of those patented "boosts" involve any inter-chip data sharing. I think they are all limited to intra-chip inter-engine sharing.

The obvious inter-chip efficiency "boost" is just a different name for "string power supply", which indeed would be new for Spondoolines. Or maybe obvious generalization: serial power connection of small parallel clusters (2-4) of chips. Much less finicky that strict serial power to properly stabilize.

[sidehack]

"To achieve those power numbers (actually a bit better then the published numbers), in addition to full custom design, we're doing some pre-computation per job, which needs the cooperation of large number of ASICs. Hence, the ASIC isn't suitable for usage in small machines."

"For now, we decided not to share more info abut the design, due to a patent we're implementing."

Could be something else, but it's completely unrelated to power supply changes.

[2112]

"To achieve those power numbers (actually a bit better then the published numbers), in addition to full custom design, we're doing some pre-computation per job, which needs the cooperation of large number of ASICs. Hence, the ASIC isn't suitable for usage in small machines."

"For now, we decided not to share more info abut the design, due to a patent we're implementing."

Could be something else, but it's completely unrelated to power supply changes.

Who do you quote? Edit: I mean, which document do you quote?

[sidehack]

A brief email conversation from last fall.

[2112]

A brief email conversation from last fall.

Oh, so I presume some internal/unpublished document from Spondoolies. My take on this is that it may be true with their implementation only. The general implementation shouldn't (or needn't) have such limitations. Or maybe there's some additional trade-off included in their design that wasn't disclosed or covered by the patents.

IIRC the SP50 drawings released showed large number of small power supplies, so my speculation about power distribution optimization was not really well-grounded.

[sidehack]

I haven't seen any documentation on anything, just what I was told in an email after I requested info about the new chip. I also have not looked over either the paper or the patent to speculate.

Request for clarification: is your "maybe obvious generalization" serial power idea any different than what Bitmain's done for string power on S4+, S5 and S7?

[Biodom]

anyone see this video?

https://www.youtube.com/watch?v=IWxn_a0dEKI

quite interesting

IBM made a graphene chip that does text messaging. Hadn't seen that. Also wasn't any real quantitative information in there, but it might be worth reading up on. Something like that might be commercially viable for IC mass production in another decade or so.

^^^ i remember reading on graphene discovery and one thing was that was quite astonishing is that the key approach was actually very lo-tech, such as peeling off a single carbon layer using scotch tape (or, more correctly, scotch tape, followed by another, etc, etc, up to a single layer). Apparently, there were NO other methods to get a single layer at that time.

[sidehack]

According to my friend who worked in a lab with atomic force microscopes, they used scotch tape on mica sheets to get atomic-smooth slide surfaces to build nanostructures on. Never woulda guessed $3 office supplies could be so useful in the mechanics of billion-dollar industries.

[2112]

Request for clarification: is your "maybe obvious generalization" serial power idea any different than what Bitmain's done for string power on S4+, S5 and S7?

I don't know the details of BitmainTech's PCBs layout nor for the fact details of any other company. I can't really answer your question. All I've seen are some prototype designs with Bitfury chips, which were parallel connections of strictly serially connected chips. The more general layout is serial connections of groups of parallel connected chips. In the simplest case of four chips:

Code:

  +--- C1 --- C2 ---+
Vdd                 Vss
  +--- C3 --- C4 ---+ 

is parallel-serial a.k.a. "string"

Code:

  +--- C1 --+-- C2 ---+
Vdd         |        Vss
  +--- C3 --+-- C4 ---+  

is serial-parallel. The 2nd is more general and easier to control and stabilize.

[sidehack]

Okay, looks like that is it. I know of some Bitfury designs that only had one chip per node (Nanofury NF6, OneString etc) but most have more than one ASIC at each voltage level, on a common plane. The Prisma was 3 chips wide, S5 two, S4+ and S7 both three wide. My BM1384 test pods are two wide, four high.

[NotFuzzyWarm]

To me 3 chips wide could/should be more stable and forgiving of chip-to-chip Vdrop vs relying so much on the caps bypassing each node.

On the cooling fan(s) OT in the BitFury thread, it does of course factor into wall plug efficiency. Saving 30W or more is an appreciable part of the power budget. Good part is if the chips themselves consume less eg around 450w then less fan power is needed to remove it hopefully making for being able to use quieter fans. Win-win all around on that point.

[kilo17]

Hoping to have some chip news soon - will keep everyone updated.

[QuintLeo]

A brief email conversation from last fall.

Oh, so I presume some internal/unpublished document from Spondoolies. My take on this is that it may be true with their implementation only. The general implementation shouldn't (or needn't) have such limitations. Or maybe there's some additional trade-off included in their design that wasn't disclosed or covered by the patents.

IIRC the SP50 drawings released showed large number of small power supplies, so my speculation about power distribution optimization was not really well-grounded.

 They were using a bunch of 1U server power supplys to come up with ENOUGH power to fuel that monster - ballpark 15KW or some such it was specced at?

 Nothing to do with power supply optimisation, EVERYTHING to do with feeding it ENOUGH power.

[sidehack]

While it's true it used a bunch of 1U server power supplies for mains conversion, that's not at all what was being discussed.

[heslo]

Hoping to have some chip news soon - will keep everyone updated.

Great news! Probably Bitmains new chip yeah?

[NotFuzzyWarm]

Hoping to have some chip news soon - will keep everyone updated.

Great news! Probably Bitmains new chip yeah?

I would think it will be about BitFury's chip.
Considering Bitmain now has (a limited supply) of their 16nm chips from TSMC it should be safe to assume that BitFury and through them their integrators are now getting their chips as well.

Since Bitmain has now set a benchmark with their s9 it will be interesting to see what BitFury's integrators come up with to match that