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Author Topic: Avalon chip  (Read 8297 times)
2112
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February 05, 2013, 01:44:05 PM
 #1

I wanted to restart the discussion from the thread that is now locked:

https://bitcointalk.org/index.php?topic=120184.msg1402474#msg1402474

I cannot quote directly, so I'm going to do a little cut and paste quotes.

Quote from: mrb
Now that we know there will be 4055 chips per wafer, and that the die area is 16mm², I can refine my math and prediction:
- each Avalon chip will have 1/10th the number of transistors of the BFL chips (16mm² at 110nm vs. 56.25mm² at 65nm)
- BFL chips are 7.5Ghash/s, therefore Avalon chips should do 0.75Ghash/s (approximately, since the clock will be somewhat different)
- an Avalon wafer will therefore provide 4055*.75 = 3040 Ghash/s of mining power
- an Avalon wafer will go into the production of about 50 Avalon devices (~60 Ghash/s each)
- the raw cost of a wafer is $4,xxx per the partially-obscured price in the TSMC document published by the team, let's say $4500, that means $90 of wafer space per Avalon device (up from my prediction of $40)
Quote from: Mikej0h
You do realize that based on your calculation for a single Avalon device, which is advertised as 66Gh/sec, they would need 88 chips.
That sounds very unlikely to me...
Quote from: 2112
For a Chinese designers 88 would be a doubly prosperous number or joy number. Sounds likely to me...

http://en.wikipedia.org/wiki/Numbers_in_Chinese_culture#Eight
Pictures of the open Avalon modules are now available:

http://bbs.btcman.com/forum.php?mod=viewthread&tid=1304

There are 80 chips per module.

Please comment, critique, criticize or ridicule BIP 2112: https://bitcointalk.org/index.php?topic=54382.0
Long-term mining prognosis: https://bitcointalk.org/index.php?topic=91101.0
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February 05, 2013, 01:46:59 PM
 #2



Each chip has about 280MH / s, this means that they are a hardcopy of a FPGA and not a full custom ASIC.
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February 05, 2013, 01:50:03 PM
 #3

I cannot quote directly, so I'm going to do a little cut and paste quotes.

To quote something in a locked thread, get the post's individual ID number (shown by hovering over the # post link), then click quote on something in your unlocked thread (this one) but change the quote= parameter to the locked thread's quote #.

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February 05, 2013, 01:51:52 PM
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Each chip has about 280MH / s, this means that they are a hardcopy of a FPGA and not a full custom ASIC.

... Proof?

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February 05, 2013, 01:57:07 PM
 #5



Each chip has about 280MH / s, this means that they are a hardcopy of a FPGA and not a full custom ASIC.

... Proof?

If it were an ASIC, would it be just one chip?

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February 05, 2013, 01:58:30 PM
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Each chip has about 280MH / s, this means that they are a hardcopy of a FPGA and not a full custom ASIC.

... Proof?

"Avalon ASIC will not be responsible for if a proper Integrated Circuit company enters the market and produce a full-custom ASIC chip. Please evaluate your mining projections properly when purchasing Avalon ASIC."
http://launch.avalon-asics.com/?page_id=778
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February 05, 2013, 02:54:05 PM
 #7

That pic was showing a meter at almost 600w... that's a bit higher than anticipated.  Can someone translate the explanation of that pic?  Is that 600w at 66GH/s?
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February 05, 2013, 03:04:29 PM
 #8

That pic was showing a meter at almost 600w... that's a bit higher than anticipated.  Can someone translate the explanation of that pic?  Is that 600w at 66GH/s?

Yeah, 600w for 66GH/s ..only 33% higher than they advertise on their site.

EDIT: I stand corrected, it looks like they finally changed the specs on their site.

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February 05, 2013, 03:06:40 PM
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That pic was showing a meter at almost 600w... that's a bit higher than anticipated.  Can someone translate the explanation of that pic?  Is that 600w at 66GH/s?

Yeah, 600w for 66GH/s ..only 33% higher than they advertise on their site.

They've changed it on their site now http://launch.avalon-asics.com/#features

Hashrate: greater than 66 Gh/s
Power Consumption: 620w@120v AC
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February 05, 2013, 03:11:18 PM
 #10

Each chip has about 280MH / s, this means that they are a hardcopy of a FPGA and not a full custom ASIC.
This "hardcopy" comment is just misinformation.

Various FPGA copy processes need to be ordered through the respective intelectual property owner, eg.

HardCopy through Altera
EasyPath through Xilinx
etc.

In case of Avalon if this was an FPGA copy they would place an order with Xilinx not with TSMC.

It clearly is a custom ASIC.

Now the adjective "full" has no well-defined meaning next to "custom ASIC". By my reading of the posts in this forum only two persons creatures are working on a full custom ASIC: bitfury and yohan yohan's cat.


The designer is watching.
The distinctive mark of a full custom designer is that his simulation result errors are narrower than the manufacturing process variance. The way I interpret the words "full custom" would mean that the designer had run an analog level simulation on BSIM (or an equivalent toolset). The error-bounds on such simulations are very narrow, in fact the proper simulation would consist of multiple simulation runs modeling various corners of the manufacturing process. This is just time consuming.

It is of course possible that some vendor really does full custom design, but deliberately spreads misinformation on this forum to hide their intellectual property.

It is also possible that some vendor is in a posession of some EDA tool that they don't have a full license and/or don't fully understand how to operate and/or don't have all the required input data for models. This would be another explanation of unusually wide error bounds on simulation.

Please comment, critique, criticize or ridicule BIP 2112: https://bitcointalk.org/index.php?topic=54382.0
Long-term mining prognosis: https://bitcointalk.org/index.php?topic=91101.0
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February 05, 2013, 03:16:39 PM
 #11



Each chip has about 280MH / s, this means that they are a hardcopy of a FPGA and not a full custom ASIC.

Avalon chip is NOT a hardcopy or something  similar.
meanwhile, it is NOT a full custom ASIC too.

Avalon ASIC is designed with standard cell.

That pic was showing a meter at almost 600w... that's a bit higher than anticipated.  Can someone translate the explanation of that pic?  Is that 600w at 66GH/s?

this is reality.



Yeah, 600w for 66GH/s ..only 33% higher than they advertise on their site.

power consumption details by actual measurement :

Chip power efficienty: ~6.6W/GHs @ 1.15 V
Module power consumption: 149W @ 20.048GHs/ 164W@ 22.560GHs
machine power consumption: 67.68G for ~595W @ 220V-AC/ ~620W @ 120V-AC

CEO of Canaan-creative, Founder of Avalon project.
https://canaan.io/
Business contact: love@canaan.io
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February 05, 2013, 03:30:11 PM
 #12



Each chip has about 280MH / s, this means that they are a hardcopy of a FPGA and not a full custom ASIC.

Avalon chip is NOT a hardcopy or something  similar.
meanwhile, it is NOT a full custom ASIC too.

Avalon ASIC is designed with standard cell.

That pic was showing a meter at almost 600w... that's a bit higher than anticipated.  Can someone translate the explanation of that pic?  Is that 600w at 66GH/s?

this is reality.



Yeah, 600w for 66GH/s ..only 33% higher than they advertise on their site.

power consumption details by actual measurement :

Chip power efficienty: ~6.6W/GHs @ 1.15 V
Module power consumption: 149W @ 20.048GHs/ 164W@ 22.560GHs
machine power consumption: 67.68G for ~595W @ 220V-AC/ ~620W @ 120V-AC

Thank you ngzhang for the clarification and info, it is appreciated!
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February 05, 2013, 03:42:09 PM
 #13

If it were an ASIC, would it be just one chip?

Generally no and especially not for "first gen" product.  The larger the die size the larger the % of chips lost due to fabrication errors. For a design like this you can't have a chip "half good" so any functional defect means a lost chip.  The size of the die is likely based on the vendor (i.e. people actually making the chip) recommendation.  

It is a tradeoff.  A single 22GH/s chip would either need to be massively parallel (i.e. one chip is designed to split the work among multiple hashing engines working in parallel (multiple nonces checked per clock cycle) or  it would need to run at an insanely high clock (to complete 22 GH/s using a single hashing engine would require a clock speed of 22 Ghz obviously impractical).

Based on the photo and specs my guess is that each Avalon chip completes a single SHA-256 double hash per clock and runs at ~275Mhz.  So if you had a board with a single chip it would use about 2W and produce complete 275 million double SHA-256 hashes per second obviously that is impractical so a board consists of 80 chips working together to produce 22 GH/s (80 * 0.275 Gh/s per chip = 22 Gh/s per board).  To do this with one chip at the same clock speed would require the chip have 80 hashing engines.  That would make the die 80 times as large. 

The entire unit is simply a controller, powersupply, and logic boards to route block headers to the individual hashing chips and "golden nonces" (diff 1 = 1 in 2^32 hashes) back to the controller for verification.  How the work gets broken up is simply a design choice you could make a 66 GH/s miner using 66,000 chips with a hashrate of 1 Mh/s ea or a single chip with a hashrate of 66 GH/s.  Everything being equal having fewer larger chips simplifies board design, assembly and production however larger chips mean higher power density (harder to cool 100W in one chip then 100W spread out over a board) and lower chip yields so neither extreme is attractive. The sweetspot tends to be in the middle. 

The next gen (not batch2, or 3 but the next design) will get more parallel.  Instead of 320 chips which have a single "hashing engine each" you could use 40 larger chips with 8 hashing engines.  If ASIC production remains competitive maybe in a few generations you will see much larger chips capable of high GH/s speed (say 20 hashing engines inside a single chip running at 800 MHz completing 16 GH/s per chip).

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February 05, 2013, 03:50:58 PM
 #14

@DeathAndTaxes

Will the "hashers working in parallel" reduce the power consumption measured in J/Hash? Or it will just reduce the cost of the chip measured in USD/Ghashes?

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February 05, 2013, 03:54:17 PM
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From the OP it is interesting to see how low prices can eventually go.  If the quote is correct then the production cost of just the chips is roughly $1 per chip (or ~$4 per GH/s).    Remember the seller has hundreds of thousands in NRE costs to overcome but they will be paid down eventually.  Lets ignore the powersupply, controller, fans, and case because the designer could just sell modules.  

PCB printing and placement ~$10 + $80 in chips plus maybe $20 in misc components (resistors, capacitors, voltage regulators) say a total SWAG of $110 per board.  Note I am not accusing the sellers of price gouging.   They did take a large risk, and have lots of NRE costs to cover.   Also they will want to retain capital to make the "next gen" unit eventually.  I am just pointing out that difficulty is going up a LOT.  People thinking no more than 10x are going to be horribly disappointed.  In the short term 30x to 50x is more likely.  In the longer term (a year or more so both Avalon and BFL have time to release their "next gen" products) 100x to 200x isn't impossible.  Why?  When sales flatline they (both companies) can cut the price and sell more.  
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February 05, 2013, 04:02:24 PM
 #16

@DeathAndTaxes

here is no personal offence, but your deduce in this thread are totally in-correct.


CEO of Canaan-creative, Founder of Avalon project.
https://canaan.io/
Business contact: love@canaan.io
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February 05, 2013, 04:04:03 PM
 #17

I am just pointing out that difficulty is going up a LOT.  People thinking no more than 10x are going to be horribly disappointed.  In the short term 30x to 50x is more likely.  In the longer term (a year or more so both Avalon and BFL have time to release their "next gen" products) 100x to 200x isn't impossible.


I agree as well, I have been doing some calculations on difficulty and I have a calendar with estimates to see if it is staying on the curve I believe we are heading on.   The next month will be crucial to give us the pace for the next 6 months.  

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February 05, 2013, 04:13:13 PM
 #18

I agree as well, I have been doing some calculations on difficulty and I have a calendar with estimates to see if it is staying on the curve I believe we are heading on.   The next month will be crucial to give us the pace for the next 6 months. 

The shape of the curve depends on how aggressive both companies can be in moving units.  For Avalon how quickly will all batch 2 customers get their units, will there be a delay on batch3, etc.  For BFL can they get out the door in Feb and once they do how many units per week can they sustain in production.  The end state is much higher difficulty it really just depends on how steep the curve is. 
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February 05, 2013, 04:13:35 PM
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@DeathAndTaxes
here is no personal offence, but your deduce in this thread are totally in-correct.

Well tell me where I am wrong. Smiley
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February 05, 2013, 04:18:43 PM
 #20

I agree as well, I have been doing some calculations on difficulty and I have a calendar with estimates to see if it is staying on the curve I believe we are heading on.   The next month will be crucial to give us the pace for the next 6 months. 

The shape of the curve depends on how aggressive both companies can be in moving units.  For Avalon how quickly will all batch 2 customers get their units, will there be a delay on batch3, etc.  For BFL can they get out the door in Feb and once they do how many units per week can they sustain in production.  The end state is much higher difficulty it really just depends on how steep the curve is. 

Precisely. The way I've been looking at it, the absolutely minimum for first gen will probably be around 250-300TH/s (tripling BFL's preorder count, adding Avalon's batch #1 and #2, and tossing in ASICMiner as well). It'll only go up from there once people see working devices, as well as Gen 2 speculation.

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