DIY PCB with AVALON: "The Quarter Stick" - Needs Help!

[samurai1200]

I was using this image for my information:
http://avalon.mystisland.org/a14.jpg

Ah, new information (to me)! This is very helpful.

I'm usually not one to speculate on such things as a chip pinout, but allten seemed eager to have more information, perhaps to move a little further on his pcb layout.

I'll agree the top pour has to be Vcor, and that 7,24,37 are most likely Vio.

Regarding your idea that the clock input is most likely a low frequency due to it not being differential, I completely agree. Though, this is weird as hell, where the heck are the oscillators? I can't see them anywhere, heh. Possibly on the other side of the PCB? That would be wierd though, considering how much empty space there is on the top, and how much more it costs to get components on both sides of the PCB.

I spy with my little eye, an XO! On the card, look at the space below the backplane connector. There is a metal can smt chip that has the writing "TXC 32.0 CBB3V" on it. Looks an awful lot like:
http://www.txccrystal.com/images/pdf/7w.pdf

If it is indeed a 32MHz signal, that would support my idea of single ended clock lines (pushed by the little 6-pin buffer lookin' guy below the xo).

[BkkCoins]

If it is indeed a 32MHz signal, that would support my idea of single ended clock lines (pushed by the little 6-pin buffer lookin' guy below the xo).

Yes, this is correct. I mentioned it back up the thread a ways. Most likely there is a PLL on the ASIC as none of the chips on board seem to be right for this (and if there was one it would be best close to the ASICs).

The cgminer driver for Avalon sets the frequency as part of the prep for each work sent so I expect that it gets shifted into the device via the serial, just before the actual work data. It seems to be a couple bytes so presumably there is a PLL register controlling frequency.

Here are the register values:

256 MHz: 0x03 0x08
270 MHz: 0x73 0x08
282 MHz: 0xd3 0x08
300 Mhz: 0x63 0x09

edit: A bit of pondering over the numbers...

Second byte is multiplier 0x08 * 32 = 256
First byte, low bits 3 is constant so probably sets something up, mode or ?.
The first byte, high bits are half of the offset added to the second byte. Not sure how that works but it does.

256 = 0*2 + 8 * 32
270 = 7*2 + 8 * 32
282 = d*2 + 8 * 32
300 = 6*2 + 9 * 32

So setting, 0xf3 0x08 should give 286 MHz.

[Bogart]

I am also very interested in joining these efforts! I am an EE hobbyist but very eager to play around with these chips. Luckily these chips are QFN, which is a godsend compared to BGA. This also means we can use OSH park for prototypes all the way up to 4 layers for cheap.

Some quick questions:

https://en.bitcoin.it/wiki/Avalon <-- is this a good repository of everything we know so far?

Has anyone stuck a scope on one of these chips and checked out the signals?

Did anyone decap the chip yet and get photos? If not, seeing as how this ic is only 110nm, we should be able to send a few chips to a decap plant and have them decap it properly and get high quality images only for a few grand. For a few grand more, they should be able to reverse engineer it a bit for us too.

I see BkkCoins has done some chip pin inspecting. Do you have any oscope close by so we can get the clock frequency? Some multimeters have a frequency counter.

Anyways, I would gladly help out designing the PCB for these chips. I have Altium on hand and can make a few prototypes. I actually wonder if someone who has an Avalon can sell one of the modular units? Then the dev's can send it to each other every few days to take turns trying to find out as much information as possible.

With my partners we bought a broken Avalon and I can check with them to provide a blade for inspection so we learn as much as possible while the specs get to us.

All the best,
Dieguito

Would you consider selling one of the hashing submodules out of it (one of the boards with the 10 ASIC chips)?

I would love to have one on hand to study also.

[E3V3A]

Great work, could some Avalon owner send us a picture of the back of the PCB?

[dieguito]

I am also very interested in joining these efforts! I am an EE hobbyist but very eager to play around with these chips. Luckily these chips are QFN, which is a godsend compared to BGA. This also means we can use OSH park for prototypes all the way up to 4 layers for cheap.

Some quick questions:

https://en.bitcoin.it/wiki/Avalon <-- is this a good repository of everything we know so far?

Has anyone stuck a scope on one of these chips and checked out the signals?

Did anyone decap the chip yet and get photos? If not, seeing as how this ic is only 110nm, we should be able to send a few chips to a decap plant and have them decap it properly and get high quality images only for a few grand. For a few grand more, they should be able to reverse engineer it a bit for us too.

I see BkkCoins has done some chip pin inspecting. Do you have any oscope close by so we can get the clock frequency? Some multimeters have a frequency counter.

Anyways, I would gladly help out designing the PCB for these chips. I have Altium on hand and can make a few prototypes. I actually wonder if someone who has an Avalon can sell one of the modular units? Then the dev's can send it to each other every few days to take turns trying to find out as much information as possible.

With my partners we bought a broken Avalon and I can check with them to provide a blade for inspection so we learn as much as possible while the specs get to us.

All the best,
Dieguito

Would you consider selling one of the hashing submodules out of it (one of the boards with the 10 ASIC chips)?

I would love to have one on hand to study also.

I have to discuss it with my partners but what I can commit to do in the meantime is that as soon as I have the broken Avalon in my power I will send pictures of every little corner so we can collectively understand how is built.

Also we have bought 10K of chips to build ASIC miners and would be glad to include an EE in our project if he can help us speed up the time to market of the machines.

All the best,
Dieguito   

[E3V3A]

Is the Avalon design related to this?

http://www.design-reuse.com/sip/blockdiagram/29355/20120816035354-main-Avalon-Bus-I2C-Controller.gif

[BkkCoins]

Is the Avalon design related to this?

No, just a coincidental use of the same name.

[E3V3A]

No, just a coincidental use of the same name.

I know about the "coincidental" name, but certainly that design seem quite standard. So, how does the Spartan-6 (FPGA) controller communicate with the Avalons, if they're not using I2C?

[BkkCoins]

No, just a coincidental use of the same name.

I know about the "coincidental" name, but certainly that design seem quite standard. So, how does the Spartan-6 (FPGA) controller communicate with the Avalons, if they're not using I2C?

In that article the Avalon being referred to is the bus protocol used by the Altera NIOS II microprocessor core. Nothing to do with the mining machine named Avalon.

As for how "our" Avalon communicates I haven't found that info yet and it may be I2C but it's not the only standard around. It could be simply serial (using an USART), or SPI or CAN bus (unlikely), or proprietary or who knows.

I favour it being a simple serial daisy chain. In that case the FPGA does very little except act as a traffic switch between the FTDI USB-Serial converter and the final selected chip sub-module. The first N bits shift into a path selector register and choose the output path for the remaining M bits. But I'm guessing. For all I know there's a microprocessor core in the FPGA making decisions and using I2C to each ASIC. I2C is a more complicated protocol that requires an I2C core or micro-controller.

The serial data sent by the driver contains a few bytes of header data for each job. miner number and asic number are part of this. Miner number would select the route to a sub-module. Avalon has 24 miners and 10 chips per miner. Since it sends this data for each job and not once at startup we can likely assume it doesn't have "intelligence" on board. Just something to route work data to each chip.

The driver sends all 10 chips work data for each job enumerated out as a long stream. This seems to point at it being ready to be fed into a long shift register chain spanning the 10 chips.

[yuppie]

Low Cost DIY ASIC Miner

Purpose:
This thread is intended for the development of a very low cost DIY open source
ASIC miner based on Avalon's chips. Hopefully, it will inspire other Bitcoin ASIC
manufactures to offer their chips as well.

Objectives:
* Get ASICs in the hands of the masses ASAP.

* Create the cheapest solution possible. The lowest possible price is the goal.
The $ per hash ratio is not expected to be the best.

* Make it simple enough that anyone with a DIY spirit can assemble one of these with
some simple low priced tools.
https://www.sparkfun.com/tutorials/category/2
DIY manufacturing may be an avenue to get these out much faster.
Expect a few hours assembly time per board.

*Make the PCB design that is not only DIY friendly, but mass production friendly as well.
It will use surface mount technology.

*Inspire more ASIC Bitcoin Mining manufactures to pop up all over the world (Decentralization).
ASIC manufacturing in general is the most complicated production process in the world.
IMO, the best thing for Bitcoin would be for ASIC Bitcoin Manufactures to be decoupled from
final product production; or at least offer their chips as well on top of their final products.

Specifications (subject to change):
* USB power source is all that is required.
* Utilizes a single Avalon ASIC
* 256+ MH/s
* 2 Watt maximum power usage
* TYPE A USB Male option on either side of the PCB
* Type B USB Female option
* More to come

Sponsors:
*Burnin - He is a serious manufacture of Bitcoin mining equipment. He has committed to helping
with the open source software/firmware to make this project function. He has started an official
thread for his miners and it's worth checking out:
https://bitcointalk.org/index.php?topic=179769.0

*Zefir - He is preordaining Avalon ASICs in smaller quantities for anyone interested:
funds: https://bitcointalk.org/index.php?topic=177827.0
Zefir is committed to helping this low cost DIY project be successful by making a small quantity
of chips available for ordering and development.

Team:
All of you! An open source design also means its open to anyone. Feel free to take the initiative
to help out in your own way. Please don't get discouraged as it may take time to figure
out where your talents fit in best. I have received an overwhelming quantity of supportive emails
and also many request to help out. I wasn't prepared for that, but now, I would like to make
a list of anyone that wants to get involved here and what they would like to bring to the table.
Shoot me ANOTHER email and I will add you name here.

"Someone42" who was the inspiration and pioneer in hardware wallets has offered his help here.
"Burnin" has also offered his help, but is also very busy as he is preparing his own miner.

Allten's Commitment:
I will engineer the schematic and the PCB. As soon as the chip specifications are available, I will
release within a week a preliminary design for feedback. I will personally manufacture enough
of these to get them in the hands of all those that will be helping with firmware/software development.
After that, a detailed tutorial will be made on how to order and produce these by yourself.

Important note: I do not want to become a distributor for these for the simple fact I would like
to have time available for other projects I'm passionate about. This is a golden opportunity for anyone
or a few people to become distributors of DIY kits and already assembled miners. I will assist anyone
to get set up for this once I've completed the tutorial.

Funding:
Sending some coins would be very helpful and greatly appreciated.
1AqEzSiw7aqZ7T53XvXMqrcnUD5tKcvJxP
What will donations cover? Enough to order the parts and PCBs for the initial boards used for development.
All extra will be used to drive bounties for software/firmware development.
I get the feeling that many have ordered chips with confidence that there will be a PCB solution
readily available before the ASICs arrive. If that is the case, consider donating up to 5% of
what you invested in chips to this project. It would sure help hurry it a long! Much of the bounty portion
may go to "burnin" as his code development for the controller portion will be shared with this project and
he is most heavily invested to make it work along with his product ASAP.

ok so how far away are we from all of this? What obstacles are in the way?

[ryepdx]

Are there any plans to make a larger miner PCB design? I have about 480 chips on the way, but no knowledge of EE. I'm hoping for something I can take to a local plant for printing and assembly, but the aim as stated in the amended OP would result in too small of a board. I don't have 480 USB ports available... 

[supwang]

A great work! But it's too complicated for me, but I will continue to pay attention to it.

[BkkCoins]

Are there any plans to make a larger miner PCB design? I have about 480 chips on the way, but no knowledge of EE. I'm hoping for something I can take to a local plant for printing and assembly, but the aim as stated in the amended OP would result in too small of a board. I don't have 480 USB ports available...  

The design I'm working on is 16 chips on a 10cm x 8cm board. Each board has a PIC USB controller but also supports I2C. This allows chaining multiple boards together so they use only one USB port. I'm targeting a 2 layer board to keep costs very low. If I run into problems with 2 layers then I'll bump up to 4 layer but that increases pcb cost by 3-4x. Right now parts cost estimate for one board is about $20 including pcb, not including ASIC, heat sink, assembly or parts shpg. ($20/16 chips is $1.25 per chip.)

I'll post my design on github eventually after final specs come out. You could panelize 8 boards on a larger 20cm x 32cm pcb for production. Then you would have 4 BIG boards total. Or whatever combination works. On each panel you would tie the sections together with I2C bus (4-wire ribbon cable), have one USB port and make a power splitter lead to distribute the 12V. 8 units using 32W each is 256W per BIG board. You could run two boards off a good 650W supply. Smaller boards give a bit more flexibility in arranging them for cooling.

I'll post more as I progress or check here:  http://github/bkkcoins
Don't expect anything until after Avalon docs are released.

[ryepdx]

Much thanks. I'll definitely keep an eye on your Github account. :-)

[loshia]

The design I'm working on is 16 chips on a 10cm x 8cm board. Each board has a PIC USB controller but also supports I2C. This allows chaining multiple boards together so they use only one USB port. I'm targeting a 2 layer board to keep costs very low. If I run into problems with 2 layers then I'll bump up to 4 layer but that increases pcb cost by 3-4x. Right now parts cost estimate for one board is about $20 including pcb, not including ASIC, heat sink, assembly or parts shpg. ($20/16 chips is $1.25 per chip.)

I'll post my design on github eventually after final specs come out. You could panelize 8 boards on a larger 20cm x 32cm pcb for production. Then you would have 4 BIG boards total. Or whatever combination works. On each panel you would tie the sections together with I2C bus (4-wire ribbon cable), have one USB port and make a power splitter lead to distribute the 12V. 8 units using 32W each is 256W per BIG board. You could run two boards off a good 650W supply. Smaller boards give a bit more flexibility in arranging them for cooling.

I'll post more as I progress or check here:  http://github/bkkcoins
Don't expect anything until after Avalon docs are released.

BkkCoins ,

Do you think that  2 layers PCb would be ok. As far as i understand 4 layers PCb is used because of chip cooling. PCB is used for cooling also

Otherwise your design looks perfect, just put a molex for 12V from PSu and we are ready to rock!

[someone42]

Here are the register values:

256 MHz: 0x03 0x08
270 MHz: 0x73 0x08
282 MHz: 0xd3 0x08
300 Mhz: 0x63 0x09

edit: A bit of pondering over the numbers...

Second byte is multiplier 0x08 * 32 = 256
First byte, low bits 3 is constant so probably sets something up, mode or ?.
The first byte, high bits are half of the offset added to the second byte. Not sure how that works but it does.

Here's another interpretation: each of those 2 byte register values can be interpreted as a little-endian integer, with bits 4 - 11 giving the core clock rate in 2 MHz increments. I would hypothesise that the 32 MHz clock is being pre-divided by 16, then multiplied by the factor given in this register. If that's true, it should be possible to tweak the clock rate in 2 MHz increments. If any of these DIY boards have a programmable power supply, then it could be just like the GPU days, with people tweaking their boards to get that extra few percent.

(As for why the clock isn't just 2 MHz to begin with, perhaps the 32 MHz is also used as a serial clock.)

Yes, when a target hash is found it outputs a serial stream. But remember there are 10 chips on each sub-module board. I believe the work is streamed in serially thru all 10 chips. I say this because that's how the driver outputs the work - as a long stream where each portion is a range of work for each chip. But when a result occurs it has to collect/monitor from all 10 chips. I would guess that a wire'OR type return path could be used as long as a collision doesn't occur, or can be detected. Otherwise you have 10 output lines coming back and each needs to polled for detecting data. I'm speculating here.

The probability of two (or more) ASICs in a set of 10 hitting a valid nonce at the same time is about 2e-18. You could OR together all 10 outputs, ignore collisions, and get away with it (you'll lose a negligible portion of valid results).

[BkkCoins]

Do you think that  2 layers PCb would be ok. As far as i understand 4 layers PCb is used because of chip cooling. PCB is used for cooling also

Otherwise your design looks perfect, just put a molex for 12V from PSu and we are ready to rock!

I'm aware of this but I think with a bundle of thermal vias under the pad the heat will be conducted directly to the heat sink on back. The FR4 material is a poor heat conductor so I can't see the internal layers really dissipating much in comparison. Without the big heat sink it would definitely be a problem and the internal layers would help. To be honest I'm not sure but I think it is worth trying. My theory is that getting the heat directly to the heat sink is better than counting on dissipation thru internal layers. I thought about using thinner FR4 material as well since that would give better heat conduction.

A 4 layer board would be more typical. I think that the specifics of this case merit looking at a 2 layer one. Not high frequencies and relatively few signals make a case for trying. If the routing ends up being too difficult I would backtrack to a 4 layer design. We'll see.

I have some MicroFit Jr connectors on hand for power (I like the small size) but I'm thinking I should use the standard MiniFit PCIe connectors. They're somewhat bigger. The adapters and Y connectors are so common it would make hooking up lots of boards very easy. For the MicroFitJr I would have to make special Y cables - kind of a hassle.

Here's another interpretation: each of those 2 byte register values can be interpreted as a little-endian integer, with bits 4 - 11 giving the core clock rate in 2 MHz increments. I would hypothesise that the 32 MHz clock is being pre-divided by 16, then multiplied by the factor given in this register. If that's true, it should be possible to tweak the clock rate in 2 MHz increments. If any of these DIY boards have a programmable power supply, then it could be just like the GPU days, with people tweaking their boards to get that extra few percent.

(As for why the clock isn't just 2 MHz to begin with, perhaps the 32 MHz is also used as a serial clock.)

The probability of two (or more) ASICs in a set of 10 hitting a valid nonce at the same time is about 2e-18. You could OR together all 10 outputs, ignore collisions, and get away with it (you'll lose a negligible portion of valid results).

Interesting. I was just guessing so I'm eagerly awaiting the docs.
I didn't even think about likelihood of collision but you're right. Though you also have to account for the timing as the serial data is 112500 baud compared to the hashing at 282 MH/s. So a lot of hashes are done during the time of 32 bits shifted out. Roughly 2500 x 9 chips. Well, still slim odds.

[loshia]

BkkCoins,

Thank you for your prompt reply! I will watch your git very closely:)

Another cooling idea. If you can design the PCB so all capacitors to be on top. We can submerge it in mineral/transformer oil and it will cool the chips down nicely. The option not to submerge capacitors will be great. As far as i know they are the only ones where rubber can be damaged from oil. The pcb to be partially submerged all asic chips and oil not to reach the capacitors
What about it?
Best

[BkkCoins]

BkkCoins,

Thank you for your prompt reply! I will watch your git very closely:)

Another cooling idea. If you can design the PCB so all capacitors to be on top. We can submerge it in mineral/transformer oil and it will cool the chips down nicely. The option not to submerge capacitors will be great. As far as i know they are the only ones where rubber can be damaged from oil. The pcb to be partially submerged all asic chips and oil not to reach the capacitors
What about it?
Best

I've heard of people doing that but I don't have the stomach for it myself. I have used water cooling on some old socket 478 mainboards and I still have 3 water blocks from this. They actually may work for this but I probably won't bother. Well, maybe, but don't know. My mini-ITX Core2Duo dissipates 30W in one spot and works with a small fan. I'm reasonably confident that spread over 16 chips, 80 cm2 of copper, and heat sinks, the same heat output can be handled by heat sinks and air flow. (I really need one of these IR temperature guns though.)

The whole non-chip side of the board will be a big GND plane that mates directly with 2 heat sinks. I can't put anything there except around the edges and up the middle between heat sinks. I expect all caps to be on top and all are ceramic anyway. Just one 12V input electrolytic to go next to power connector. My plan is to bring the 1.2V down each side to the chips and run all the data lines up the middle. By having a centre channel between 2 heat sinks on back I can place the PIC and oscillator there and use both layers for vias. I can't run vias under the heat sink. Well, this what I'm thinking right now.

[loshia]

BkkCoins,

Thank you for your prompt reply! I will watch your git very closely:)

Another cooling idea. If you can design the PCB so all capacitors to be on top. We can submerge it in mineral/transformer oil and it will cool the chips down nicely. The option not to submerge capacitors will be great. As far as i know they are the only ones where rubber can be damaged from oil. The pcb to be partially submerged all asic chips and oil not to reach the capacitors
What about it?
Best

I've heard of people doing that but I don't have the stomach for it myself. I have used water cooling on some old socket 478 mainboards and I still have 3 water blocks from this. They actually may work for this but I probably won't bother. Well, maybe, but don't know. My mini-ITX Core2Duo dissipates 30W in one spot and works with a small fan. I'm reasonably confident that spread over 16 chips, 80 cm2 of copper, and heat sinks, the same heat output can be handled by heat sinks and air flow. (I really need one of these IR temperature guns though.)

The whole non-chip side of the board will be a big GND plane that mates directly with 2 heat sinks. I can't put anything there except around the edges and up the middle between heat sinks. I expect all caps to be on top and all are ceramic anyway. Just one 12V input electrolytic to go next to power connector. My plan is to bring the 1.2V down each side to the chips and run all the data lines up the middle. By having a centre channel between 2 heat sinks on back I can place the PIC and oscillator there and use both layers for vias. I can't run vias under the heat sink. Well, this what I'm thinking right now.

Sexy I am refreshing your git already