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Question: Wich FPGA shall be used on our prototype ?
Xilinx Spartan 6 LX 150 - 17 (70.8%)
Altera Cyclone IV 75k - 7 (29.2%)
Total Voters: 24

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Author Topic: Modular FPGA Miner Hardware Design Development  (Read 112153 times)
O_Shovah
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July 17, 2011, 06:28:50 PM
 #301

Thank you
for the tipps.

I ve routed the FPGA so far. Next is the MSP and capacitors.

@ li_ganyi  i  will not use vias under pins any more seems it also works without.

@ Olaf.Mandel: how are you doing with your routing  any changes so far ?
 

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makomk
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July 17, 2011, 06:43:43 PM
 #302

The 8mil line width and line spacing are a problem, though: I cannot get an 8mil wire between two pads of the FPGAs: the clearance is too small. This problem can be solved by using more vias and routing everything on the other layers, but is is less than ideal.
Out of interest, is 6mil trace + 6mil space good enough? That's what Laen's PCB group order for hobbyists provides, and supposedly someone's done a PCB with this pitch of BGA on that service. Of course, the turnaround times on that are probably less than ideal, especially if you're not in the US.

  • What does pcbcart mean when they ask for the "Min. Annular Ring"? The width of the ring on one side ((D_via-D_hole)/2) or the sum of the width on both sides of the hole (D_via-D_hole)?
I'm pretty sure annular ring is generally defined as the width of the copper ring on each side, so D_via = D_hole + 2 * annular ring.

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Olaf.Mandel
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July 17, 2011, 08:12:35 PM
 #303

[...]
@ Olaf.Mandel: how are you doing with your routing  any changes so far ?

Unfortunately, nothing yet. I hope to do more tomorrow. I missed your post that sets the min width and clearance: found it just now. pcbcart can also do 0.15mm(=6mil) each. If you reduce the pad diameter to 0.4mm, then 0.2mm(=8mil) wire thickness and 0.15mm(=6mil) clearance are possible. But if you use 0.5mm pads, you need to use 0.15mm(=6mil) for the wire thickness.

On a related topic: what is the correct layer setup string in Eagle? I can only do vias from all layers to the top. I also need vias from layer 2 to the bottom. So an "all layers to top and all layers to bottom" setting is needed.
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July 17, 2011, 08:28:02 PM
 #304

Is any more help needed to support this development? I am an electrical engineer with >8 years of embedded experience and have worked with USB, CPLDs, FPGAs, and a slew of microcontrollers (MSP430, PIC, ARM/LPC, etc). I also have >8 years of schematic/PCB design experience and have designed with BGA (I use Altium for my PCB designs). Let me know!
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July 17, 2011, 08:32:23 PM
 #305

Is any more help needed to support this development? I am an electrical engineer with >8 years of embedded experience and have worked with USB, CPLDs, FPGAs, and a slew of microcontrollers (MSP430, PIC, ARM/LPC, etc). I also have >8 years of schematic/PCB design experience and have designed with BGA (I use Altium for my PCB designs). Let me know!

Would be nice to have an extra pair of eyes to check the work before we send it out for production, sure could use some layout optimization as well. Are you good with coding? We'd preferably want a little bit to code to run some tests on the fresh hardware that rolls out, I'd suppose you'd need to wait for more routing details to come up before you can do anything though.

Do you think adding 1-2 debug LEDs will be useful? Or maybe testpoints.

We haven't sorted out how best to share updates, I have done up the power supply section (at least the schematic).

Currently active on Custom FPGA board https://bitcointalk.org/index.php?topic=37904.0
And on X6*** FPGA board https://bitcointalk.org/index.php?topic=40058.0
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O_Shovah
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July 17, 2011, 08:52:26 PM
 #306

Is any more help needed to support this development? I am an electrical engineer with >8 years of embedded experience and have worked with USB, CPLDs, FPGAs, and a slew of microcontrollers (MSP430, PIC, ARM/LPC, etc). I also have >8 years of schematic/PCB design experience and have designed with BGA (I use Altium for my PCB designs). Let me know!

Your help is very welcome.

As li_gangyi already said you could check up on our design so far. Especially i would like you to give a comment on our current BUS system wich is crucial to the project.Eg the MSP430 would need your attention.

I dont know how much time you are abled or willing to invest into our development. But having someone with higher experience to backcheck the works and maybe even to come up wit an own layout (I also use Altium so i could look it up) would be a great help.

So i hope you to become one of our frequently active developers. Smiley

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July 17, 2011, 09:08:31 PM
 #307

I can check what you have. I have time after my day job (product design; company has factory in China) and am more then willing to help with what I can.

For debug, it is best to have at least 1 LED but more would be great (this way you indicate breakpoints easier using a morse code or binary method). Test points are essential especially if this device has not been fully verified before full production. In production it is useful to have so that you can automate the test using a "bed of nails" tester. Are you in the EVT, DVT, or PVT stage (engineering validation - design is being prototyped and initial kinks worked out; design validation - prototype works now checking to see if it works well with repeated testing (etc) and initial manufacturing issues are found/fixed; or production validation - testing the final manufacturability/production)?

I design programming and test fixtures for the products that I work on and can help with that as well. I am well versed in ASM and C - what code is complete for the MSP (if any)? What specific functions need to be added, etc?
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July 17, 2011, 09:57:05 PM
 #308

I can check what you have. I have time after my day job (product design; company has factory in China) and am more then willing to help with what I can.

For debug, it is best to have at least 1 LED but more would be great (this way you indicate breakpoints easier using a morse code or binary method). Test points are essential especially if this device has not been fully verified before full production. In production it is useful to have so that you can automate the test using a "bed of nails" tester. Are you in the EVT, DVT, or PVT stage (engineering validation - design is being prototyped and initial kinks worked out; design validation - prototype works now checking to see if it works well with repeated testing (etc) and initial manufacturing issues are found/fixed; or production validation - testing the final manufacturability/production)?

I design programming and test fixtures for the products that I work on and can help with that as well. I am well versed in ASM and C - what code is complete for the MSP (if any)? What specific functions need to be added, etc?

We're still during the initial design phase, currently dealing with the PCB. I don't think any µC code has been written so far.

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O_Shovah
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July 17, 2011, 09:58:04 PM
 #309

Im happy to hear that.

Adding leds shouldn't be a problem.You just have to tell us how many you would consider best and how to add them into the design.

There hasn't been any prototype so far and there are still some parts to be design finalised ( Bus system,Power supply,....).The BUS system is currently thought to consist of USB, SPI and bitbanging JTAG with the MSP430 in oder to talk to the FPGA and the USB connection on the DIMM as also the Motherboard.

Considering this newspost : http://asicminer.net/?p=58 we should also think of a way to make our design capable of processing more than just the bitcoin hashes. (more IO's connected ?) Just as a fail back, to keep it worthy, even if ASIC would rush the market now(altough i still consider this offer quite fishy).

There hasn't been done anything on the software side so far.

I asume you get the most things already finalised in my firstpost.So feel free to comment on those.   

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July 17, 2011, 10:14:52 PM
 #310

Sounds good. I will review thread history tonight to see what has been done (decisions, links, etc). I do agree that adding in support for future expansion would be nice, since this could be a nice training/development platform as well as for the BTC market. I will post any recommendations on this thread. What is the time line - when are you expecting to hit the PCB house for the first run?

I am trying to contact the admin/owner of the asicminer site through reddit as I have engineers in China near where his production/design house is located. The cost that he has mentioned on the website is $250*5000 ASICs which would place the total cost around $1.25million, BUT that is the sell cost (profit, etc). To build a custom ASIC you would need around $1million - to build a semi-custom (pre-done core, load your code onto their design to fit, etc) it would cost around $500K. It is possible to do but I do not know if you would see the high hash rates that he is claiming - especially since he is VERY quiet on any specifications.
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July 17, 2011, 10:39:11 PM
 #311

Sounds good. I will review thread history tonight to see what has been done (decisions, links, etc). I do agree that adding in support for future expansion would be nice, since this could be a nice training/development platform as well as for the BTC market. I will post any recommendations on this thread. What is the time line - when are you expecting to hit the PCB house for the first run?

Currently there is no specified deadline.I just keep pushing everybody forward as i can Wink. I would appreciate it if we could a least get to a prototype stage minimum end of this summer, or do you consider this difficult?

In the end, the deadline is set by the arrival of any other, both cost per Mhash and Mhash per watt, effective solution. So generaly speaking any ASIC chips being released in huge numbers.(Altough i would finish this project anyway as this is "our own" solution)       

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July 18, 2011, 01:52:10 AM
 #312

That deadline is reasonable for a prototype unit that is in the middle of testing and firmware bringup. I do not anticipate many issues with this type of design as it is a straight FGPA with ucontroller. Were any of the individual functions tested separately at least (power bus, etc) with proper loading? If not, we should do this as re-spinning the PCB would not be cost effective if there is a major issue on those smaller functions. I have a DC load tester (constant voltage or current) here as well as a decent scope that we can use.
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July 18, 2011, 05:48:24 AM
 #313


Does anyone know what the cost of these 28nm Artix 7 chips are?  I've been looking through and the XC7A350T looks promising with 350k LUs. From the text on the site it looks like they're using this chip to replace the Spartan 6's.

The idea of being able to slap 8+ of those chips on a 1x PCI-E board appeals to me. From my figures the code should be able to be unrolled 3-4 times per chip giving a theoretical processing power of 1ghash/s per chip. Since the spartan 6 is running at about 66% efficiency compared to it's theoretical values. I figure the XC7A350T current real world values would be around 600mhash/s per chip.

I sent an email query off asking for pricing information but have not heard back yet.

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July 18, 2011, 06:59:18 AM
 #314

Does anyone know what the cost of these 28nm Artix 7 chips are?  I've been looking through and the XC7A350T looks promising with 350k LUs. From the text on the site it looks like they're using this chip to replace the Spartan 6's.
 

I asume their cost to be prohibitive(remember we want to create a system with low entry investions) but the most resticting feature is their avaidability wich is said to be even worse.I addtition we would need a full commercial license for ISE, so lets please stick with the FPGA we have voted on unless you get a highly competetive price quote.
Just for comparison a similar board you quoted exists already and is ~8500 Euro each.
Edit:I see they tell the price to be "at lower price points than Spartan®-6 FPGAs" but still we may use them on a sucessor to this project not now.

That deadline is reasonable for a prototype unit that is in the middle of testing and firmware bringup. I do not anticipate many issues with this type of design as it is a straight FGPA with ucontroller. Were any of the individual functions tested separately at least (power bus, etc) with proper loading? If not, we should do this as re-spinning the PCB would not be cost effective if there is a major issue on those smaller functions. I have a DC load tester (constant voltage or current) here as well as a decent scope that we can use.

No there hasn't been any testing of any real components so far.
I agreed we should individually test segments of our setup.Power supply should be easiest to do.
Maybe Li_gangyi could post his desired setup so you may have a look on it.

Further the BUS system needs individual testing.

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July 18, 2011, 07:33:56 AM
 #315

Here's the PSU I've layed out.

http://www.dropbox.com/gallery/19035447/1/FPGA?h=b7ac9a

http://dl.dropbox.com/u/19035447/FPGA%20PSU.sch

I've split up the Vccint reg for easier layout, thermal management and headroom.
Vccaux and Vccio are both tied together and set at 2.5v, I think if we want to use the board not just for Bitcoin mining, we might have to split the supplies, or at least filter the Vccaux with ferrite beads.

I've left alot of headroom for this design, the modules are also easy to use, very few external parts, and are hand solderable if we decide to prototype or change anything.

Currently active on Custom FPGA board https://bitcointalk.org/index.php?topic=37904.0
And on X6*** FPGA board https://bitcointalk.org/index.php?topic=40058.0
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July 18, 2011, 07:59:23 AM
 #316

I see the drawing looks good so far.

But the eagle .sch file seems to be corrupted at least my eagle says so.
Maybe you check this please.

Again i would like to advertise the use of my dropbox folder ( or someones else but only one ) just need to have your email.


In addition we should further investigate on the matter wich changes to our currently desired setup are nessesary to allow the use of different programms than for bitcoin.

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July 18, 2011, 08:29:07 AM
 #317

Does anyone know what the cost of these 28nm Artix 7 chips are?  I've been looking through and the XC7A350T looks promising with 350k LUs. From the text on the site it looks like they're using this chip to replace the Spartan 6's.
Right now they're not available at any price as far as I can tell; initial samples are meant to be shipping in the first quarter of 2012, with production quantities available who-know-how-long later. This is also wildly off-topic though, given that this thread's about building boards with actual FPGAs that are available now.

Expect to fit at least 4 hashers in the XC7A350T unless Xilinx have done something daft in the design again like they did with Spartan-6, which is entirely possible. I have no idea about clock speeds; estimating that would require a full ISE license.

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senseless
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July 18, 2011, 09:03:54 AM
 #318

This is also wildly off-topic though, given that this thread's about building boards with actual FPGAs that are available now.

Apologies, had no idea that the chip was not yet on the market. I guess the spartan 6 is as good as it gets for the time being.



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July 18, 2011, 09:22:51 AM
 #319

Apologies, had no idea that the chip was not yet on the market. I guess the spartan 6 is as good as it gets for the time being.

It took 2 years for the Spartan-6 to become widely available in numbers since announcement, so the Artix-7 is somewhere on the horizon. Interesting to look at, but will be out of reach probably until 2013.

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July 18, 2011, 11:30:44 AM
 #320

Added updated layout + schematic files for the PSU and BOM to the dropbox, I think that is alot easier to use then Github for this.

Currently active on Custom FPGA board https://bitcointalk.org/index.php?topic=37904.0
And on X6*** FPGA board https://bitcointalk.org/index.php?topic=40058.0
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